參數(shù)資料
型號： AM79C961AVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 96/206頁
文件大?。?/td> 1507K
代理商： AM79C961AVIW
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96
Am79C961A
PCNET-ISA II CONTROLLER REGISTERS
The PCnet-ISA II controller implements all LANCE
(Am7990) registers, plus a number of additional regis-
ters. The PCnet-ISA II controller registers are compat-
ible with the original LANCE, but there are some places
where previously reserved LANCE bits are now used
by the PCnet-ISA II controller. If the reserved LANCE
bits were used as recommended, there should be no
compatibility problems.
Register Access
Internal registers are accessed in a two-step operation.
First, the address of the register to be accessed is writ-
ten into the register address port (RAP). Subsequent
read or write operations will access the register pointed
to by the contents of the RAP. The data will be read
from (or written to) the selected register through the
data port, either the register data port (RDP) for control
and status registers (CSR) or the ISACSR register data
port (IDP) for ISA control and status registers
(ISACSR).
RAP: Register Address Port
Bit
Name
Description
15-7
RES
Reserved locations. Read and
written as zeroes.
Register Address Port select.
Selects the CSR or ISACSR
location to be accessed. RAP is
cleared by RESET.
6-0
RAP
Control and Status Registers
CSR0: PCnet-ISA II Controller Status Register
Bit
Name
Description
15
ERR
Error is set by the ORing of
BABL,
CERR,
MERR. ERR remains set as long
as any of the error flags are true.
ERR is read only; write opera-
tions are ignored.
Babble is a transmitter time-out
error. It indicates that the trans-
mitter has been on the channel
longer than the time required to
send
the
maximum
frame. BABL will be set if 1519
bytes or greater are transmitted.
When BABL is set, IRQ is as-
serted if IENA = 1 and the mask
bit BABLM (CSR3.14) is clear.
BABL assertion will set the ERR
bit.
BABL is set by the MAC layer
and cleared by writing a
“
1".
Writing a
“
0" has no effect. BABL
MISS,
and
14
BABL
length
is cleared by RESET or by set-
ting the STOP bit.
Collision Error indicates that the
collision inputs to the AUI port
failed to activate within 20 net-
work bit times after the chip ter-
minated
transmission
Test). This feature is a transceiv-
er test feature. CERR will be set
in 10BASE-T mode during
transmit if in Link Fail state.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
CERR is set by the MAC layer
and cleared by writing a
“
1".
Writing a
“
0" has no effect.
CERR is cleared by RESET or
by setting the STOP bit.
Missed Frame is set when PC-
net-ISA II controller has lost an
incoming receive frame because
a Receive Descriptor was not
available. This bit is the only in-
dication that receive data has
been lost since there is no re-
ceive descriptor available for
status information.
When MISS is set, IRQ is
asserted if IENA = 1 and the
mask bit MISSM (CSR3.12) is
clear. MISS assertion will set the
ERR bit.
MISS is set by the Buffer Man-
agement Unit and cleared by writ-
ing a
“
1". Writing a
“
0" has no
effect. MISS is cleared by RESET
or by setting the STOP bit.
Memory Error is set when PC-
net-ISA II controller is a bus
master and has not received
DACK assertion after 50
μ
s after
DRQ assertion. Memory Error
indicates that PCnet-ISA II con-
troller is not receiving bus mas-
tership in time to prevent over-
flow/underflow conditions in the
receive and transmit FIFOs.
(MERR indicates a slightly differ-
ent condition for the LANCE; for
the LANCE MERR occurs when
READY has not been asserted
25.6
μ
s after the address has
been asserted.)
When MERR is set, IRQ is as-
serted if IENA = 1 and the mask
bit MERRM (CSR3.11) is clear.
MERR assertion will set the
ERR bit.
13
CERR
(SQE
12
MISS
11
MERR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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