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參數(shù)資料
| 型號(hào)： | AM79C961AVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 196/206頁(yè) |
| 文件大小： | 1507K |
| 代理商： | AM79C961AVIW |
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196
Am79C961A
3. Assume that instead of the expected 1060 byte
frame, a 100 byte frame arrives, because there was
an error in the network, or because this is the last
frame in a file transmission sequence, or perhaps
because it is an acknowledge frame.
*
** Same as note in case 2 above, except that in this case, it is very unlikely that the driver can respond to the interrupt and get the
pointer from the application before the PCnet-ISA II controller has completed its poll of the next descriptors. This means that for
almost all occurrences of this case, the PCnet-ISA II controller will not find the OWN bit set for this descriptor and therefore, the
ENP bit will almost always contain the old value, since the PCnet-ISA II controller will not have had an opportunity to modify it.
*** Note that even though the PCnet-ISA II controller will write a ZERO to this ENP location, the software should treat the location
as a don
’
t care, since after finding the ENP=1 in descriptor number 2, the software should ignore ENP bits until it finds the
next STP=1.
ENP or ERR
Buffer Size Tuning
For maximum performance, buffer sizes should be
adjusted depending upon the expected frame size and
the values of the interrupt latency and application call
latency. The best driver code will minimize the CPU
utilization while also minimizing the latency from frame
end on the network to frame sent to application from
driver (frame latency). These objectives are aimed at
increasing throughput on the network while decreasing
CPU utilization.
Note that the buffer sizes in the ring may be altered at
any time that the CPU has ownership of the corre-
sponding descriptor. The best choice for buffer sizes
will maximize the time that the driver is swapped out,
while minimizing the time from the last byte written by
the PCnet-ISA II controller to the time that the data is
passed from the driver to the application. In the
diagram, this corresponds to maximizing S0, while min-
imizing the time between C9 and S8. (The timeline
happens to show a minimal time from C9 to S8.)
Note that by increasing the size of buffer number 1, we
increase the value of S0. However, when we increase
the size of buffer number 1, we also increase the value
of S4. If the size of buffer number 1 is too large, then
the driver will not have enough time to perform tasks
S2, S3, S4, S5 and S6. The result is that there will be
delay from the execution of task C9 until the execution
of task S8. A perfectly timed system will have the
values for S5 and S7 at a minimum.
An average increase in performance can be achieved if
the general guidelines of buffer sizes in Figure 2 is fol-
lowed. However, as was noted earlier, the correct sizing
for buffers will depend upon the expected message size.
There are two problems with relating expected message
size with the correct buffer sizing:
1. Message sizes cannot always be accurately
predicted, since a single application may expect
different message sizes at different times, therefore,
the buffer sizes chosen will not always maximize
throughput.
2. Within a single application, message sizes might be
somewhat predictable, but when the same driver is
to be shared with multiple applications, there may
not be a common predictable message size.
Additional problems occur when trying to define the
correct sizing because the correct size also depends
upon the interrupt latency, which may vary from system
to system, depending upon both the hardware and the
software installed in each system.
In order to deal with the unpredictable nature of the
message size, the driver can implement a self tuning
Descriptor
Number
Before the Frame Arrived
After the Frame Has Arrived
Comments
(After Frame Arrival)
OWN
STP
ENP*
OWN
STP
ENP*
1
1
1
X
0
1
1
Bytes 1
–
100
2
1
0
X
0
0
0***
Discarded buffer
3
0
0
X
0
0
**
Discarded buffer
4
1
1
X
1
1
X
Controller
’
s current location
5
1
0
X
1
0
X
Not yet used
6
0
0
X
0
0
X
Not yet used
etc.
1
1
X
1
1
X
Not yet used
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am79C965A | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C965A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
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