- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C961AVIW (ADVANCED MICRO DEVICES INC) PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA PDF資料下載
參數(shù)資料
| 型號： | AM79C961AVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 47/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVIW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁
Am79C961A
47
Bus Slave Mode
System Interface
The Bus Slave mode is the other fundamental operat-
ing mode available on the PCnet-ISA II controller.
Within the Bus Slave mode, the PCnet-ISA II can be
programmed for a Shared Memory or Programmed I/O
architecture. In the Bus Slave mode the PCnet-ISA II
controller uses the same descriptor and buffer architec-
ture as in the Bus Master mode, but these data struc-
tures are stored in a static RAM controlled by the
PCnet-ISA II controller. When operating with the
Shared Memory architecture, the local SRAM is visible
as a memory resource on the PC which can be
accessed through memory cycles on the ISA bus inter-
face. When operating with the Programmed I/O archi-
tecture, the local SRAM is accessible through I/O
cycles on the ISA bus. Specifically, the SRAM is acces-
sible using the RAP and IDP I/O ports to access the
ISACSR0 and ISACSR1 registers, which serve as the
SRAM Data port and SRAM Address Pointer port,
respectively.
In the Bus Slave mode, the PCnet-ISA II registers and
optional Ethernet physical address PROM look the
same and are accessed in the same way as in the Bus
Master mode.
The Boot PROM is selected by an external device
which drives the Boot PROM Address Match (BPAM)
input to the PCnet-ISA II controller. The PCnet-ISA II
controller can perform two 8-bit accesses from the 8-bit
Boot PROM and present 16-bits of data to accommo-
date 16 bit read accesses on the ISA bus.
When using the Shared Memory architecture mode,
access to the local SRAM works the same way as
access to the Boot PROM, with an external device gen-
erating the Shared Memory Address Match (SMAM)
signal and the PCnet-ISA II controller performing the
SRAM read or write and the 8/16 bit data conversion.
External logic must also drive MEMCS16 appropriately
for the 128Kbyte segment decoded from the LA[23:17]
signals.
The Programmed I/O architecture mode uses the RAP
and IDP ports to allow access to the local SRAM
hence, external address decoding is not necessary and
the SMAM pin is not used in Programmed I/O architec-
ture mode (SMAM should be tied HIGH in the Pro-
grammed I/O architecture mode). Similar to the Shared
Memory architecture mode, in the Programmed I/O ar-
chitecture mode, 8/16 bit conversion occurs when 16
bit reads and writes are performed on the SRAM Data
Port (ISACSR1).
Converting the local SRAM accesses from 8-bit cycles
to 16-bit cycles allows use of the much faster 16-bit
cycle timing while cutting the number of bus cycles in
half. This raises performance to more than 400% of
what could be achieved with 8-bit cycles. When the
Shared Memory architecture mode is used, converting
boot PROM accesses to 16-bit cycles allows the two
memory resources to be in the same 128 Kbyte block
of memory without a clash between two devices with
different data widths.
The PCnet-ISA II prefetches data from the SRAM to
allow fast, minimum wait-state read accesses of con-
secutive SRAM addresses. In both the Shared Memory
architecture and the Programmed I/O architecture,
prefetch data is read from a speculated address that
assumes that successive reads in time will be from
adjacent ascending addresses in the SRAM. At the
beginning of each SRAM read cycle, the PCnet-ISA II
determines whether the prefetched data can be
assumed to be valid. If the prefetched data can be
assumed to be valid, it is driven onto the ISA bus
without inserting any wait states. If the prefetched data
cannot be assumed to be valid, the PCnet-ISA II will in-
sert wait states into the ISA bus read cycle until the
correct word is read from the SRAM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am79C965A | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C965A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。