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參數(shù)資料
| 型號： | AM79C961AVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 77/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVIW |
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Am79C961A
77
ues for approximately 1.5 bit times after the last
LOW-to-HIGH transition on CI
±
.
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with
the values 1010b. Clock is phase-locked to the nega-
tive transition at the bit cell center of the second
“
0" in
the pattern.
Since data is strobed at 1/4 bit time, Manchester tran-
sitions which shift from their nominal placement
through 1/4 bit time will result in improperly decoded
data. With this as the criteria for an error, a definition of
“
Jitter Handling
”
is:
The peak deviation approaching or crossing
1/4 bit cell position from nominal input transi-
tion, for which the MENDEC section will
properly decode data.
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which con-
nects the DTE to a MAU. The differential interface pro-
vided by the PCnet-ISA II controller is fully compliant
with Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).
After the PCnet-ISA II controller initiates a transmis-
sion, it will expect to see data
“
looped-back
”
on the DI
±
pair (when the AUI port is selected). This will internally
generate a
“
carrier sense
”
, indicating that the integrity
of the data path to and from the MAU is intact, and that
the MAU is operating correctly. This
“
carrier sense
”
sig-
nal must be asserted within sometime before end of
transmission. If
“
carrier sense
”
does not become active
in response to the data transmission, or becomes inac-
tive before the end of transmission, the loss of carrier
(LCAR) error bit will be set in the Transmit Descriptor
Ring (TMD3, bit 11) after the packet has been
transmitted.
Twisted Pair Transceiver (T-MAU)
This section describes operation of the T-MAU when
operating in the Half Duplex mode. When in Half
Duplex mode, the T-MAU implements the Medium
Attachment Unit (MAU) functions for the Twisted Pair
Medium as specified by the supplement to IEEE 802.3
standard (Type 10BASE-T). When operating in Full
Duplex mode, the MAC engine behavior changes as
described in the Full Duplex Operation section. The
T-MAU provides twisted pair driver and receiver cir-
cuits, including on-board transmit digital predistortion
and receiver squelch, and a number of additional fea-
tures including Link Status indication, Automatic
Twisted Pair Receive Polarity Detection/Correction and
Indication, Receive Carrier Sense, Transmit Active and
Collision Present indication.
Twisted Pair Transmit Function
The differential driver circuitry in the TXD
±
and TXP
±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted Pair cable, as specified
by the 10BASE-T supplement to the IEEE 802.3 Stan-
dard. The transmit function for data output meets the
propagation delays and jitter specified by the standard.
Twisted Pair Receive Function
The receiver complies with the receiver specifications
of the IEEE 802.3 10BASE-T Standard, including noise
immunity and received signal rejection criteria (
‘
Smart
Squelch
’
). Signals meeting these criteria appearing at
the RXD
±
differential input pair are routed to the
MENDEC. The receiver function meets the propagation
delays and jitter requirements specified by the stan-
dard. The receiver squelch level drops to half its thresh-
old value after unsquelch to allow reception of
minimum amplitude signals and to offset carrier fade in
the event of worst case signal attenuation conditions.
Note that the 10BASE-T Standard defines the receive
input amplitude at the external Media Dependent Inter-
face (MDI). Filter and transformer loss are not speci-
fied. The T-MAU receiver squelch levels are designed
to account for a 1 dB insertion loss at 10 MHz for the
type of receive filters and transformers usually used.
Normal 10BASE-T compatible receive thresholds are
invoked when the LRT bit (CSR15, bit 9) is LOW. When
the LRT bit is set, the Low Receive Threshold option is
invoked, and the sensitivity of the T-MAU receiver is
increased. Increasing T-MAU sensitivity allows the use
of lines longer than the 100 m target distance of stan-
dard 10BASE-T (assuming typical 24 AWG cable).
Increased receiver sensitivity compensates for the
increased signal attenuation caused by the additional
cable distance.
However, making the receiver more sensitive means
that it is also more susceptible to extraneous noise, pri-
marily caused by coupling from co-resident services
(crosstalk). For this reason, end users may wish to
invoke the Low Receive Threshold option on 4-pair
cable only. Multi-pair cables within the same outer
sheath have lower crosstalk attenuation, and may allow
noise emitted from adjacent pairs to couple into the
receive pair, and be of sufficient amplitude to falsely
unsquelch the T-MAU.
Link Test Function
The link test function is implemented as specified by
10BASE-T standard. During periods of transmit pair
inactivity,
’
Link beat pulses
’
will be periodically sent over
the twisted pair medium to constantly monitor medium
integrity.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C965A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
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