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參數(shù)資料
| 型號： | AM79C961AVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 107/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVIW |
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Am79C961A
107
11-0
CRBC
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD2 of the current
receive descriptor.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR42-43: Current Transmit Status and Byte
Count
Bit
Name
Description
31-24 CXST
Current Transmit Status. This
field is a copy of bits 15:8 of
TMD1 of the current transmit
descriptor.
Read/write accessible only when
STOP or SPND bits are set.
Reserved locations. Written as
zero and read as undefined.
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD2 of the current
transmit descriptor.
Read/write accessible only when
STOP or SPND bits are set.
23-12
RES
11-0
CXBC
CSR44-45: Next Receive Status and Byte Count
Bit
Name
Description
31-24
NRST
Next Receive Status. This field
is a copy of bits 15:8 of RMD1 of
the next receive descriptor.
Read/write accessible only when
STOP or SPND bits are set.
Reserved locations. Written as
zero and read as undefined.
Next Receive Byte Count. This
field is a copy of the BCNT field
of RMD2 of the next receive
descriptor.
Read/write accessible only when
STOP or SPND bits are set.
23-12
RES
11-0
NRBC
CSR46: Poll Time Counter
Bit
Name
Description
15-0
POLL
Poll Time Counter. This counter
is incriminated by the PCnet-ISA
II controller microcode and is
used to trigger the descriptor
ring polling operation of the PC-
net-ISA II controller.
Read/write accessible only when
STOP or SPND bits are set.
CSR47: Polling Interval
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zero and read as undefined.
Polling Interval. This register
contains the time that the PC-
net-ISA II controller will wait be-
tween
successive
operations. The POLLINT value
is expressed as the two
’
s com-
plement of the desired interval,
where each bit of POLLINT rep-
resents one-half of an XTAL1
period of time. POLLINT[3:0] are
ignored. (POLINT[16] is implied
to be a one, so POLLINT[15] is
significant, and does not repre-
sent the sign of the two
’
s
complement POLLINT value.)
The default value of this register
is 0000. This corresponds to a
polling interval of 32,768 XTAL1
periods. The POLINT value of
0000 is created during the micro-
code initialization routine, and
therefore might not be seen when
reading CSR47 after RESET.
If the user desires to program a
value for POLLINT other than
the default, then the correct
procedure is to first set INIT only
in CSR0. Then, when the initial-
ization sequence is complete,
the user must set STOP in
CSR0. Then the user may write
to CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000 in CSR47 will be
overwritten with the desired user
value.
Read/write
accessible
when STOP or SPND bits are
set.
15-0 POLLINT
polling
only
CSR48-49: Temporary Storage
Bit
Name
Description
31-0
TMP0
Temporary Storage location.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR50-51: Temporary Storage
Bit
Name
Description
31-0
TMP1
Temporary Storage location.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C965A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
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