參數(shù)資料
型號： AM79C961AVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 109/206頁
文件大?。?/td> 1507K
代理商： AM79C961AVIW
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Am79C961A
109
CSR70-71: Temporary Storage
Bit
Name
Description
31-0
TMP8
Temporary Storage location.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR72: Receive Ring Counter
Bit
Name
Description
15-0
RCVRC
Receive Ring Counter location.
Contains a Two
’
s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor; a two
’
s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR74: Transmit Ring Counter
Bit
Name
Description
15-0
XMTRC
Transmit Ring Counter location.
Contains a Two
’
s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor; a two
’
s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR76: Receive Ring Length
Bit
Name
Description
15-0
RCVRL
Receive Ring Length. Contains
the Two
’
s complement of the
receive descriptor ring length.
This register is initialized during
the PCnet-ISA II controller initial-
ization routine based on the
value in the RLEN field of the ini-
tialization block. This register
can be manually altered; the
actual receive ring length is
defined by the current value in
this register.
Read/write
when STOP or SPND bits are
set.
accessible
only
CSR78: Transmit Ring Length
Bit
Name
Description
15-0
XMTRL
Transmit Ring Length. Contains
the two
’
s complement of the
transmit descriptor ring length.
This register is initialized during
the PCnet-ISA II controller initial-
ization routine based on the
value in the TLEN field of the ini-
tialization block. This register
can be manually altered; the
actual transmit ring length is
defined by the current value in
this register.
Read/write
accessible
when STOP or SPND bits are
set.
only
CSR80: Burst and FIFO Threshold Control
Bit
Name
Description
15-14
RES
Reserved locations. Read as
ones. Written as zero.
Receive
FIFO
RCVFW controls the point at
which ISA bus receive DMA is
requested in relation to the num-
ber of received bytes in the
receive FIFO. RCVFW specifies
the number of bytes which must
be present (once the frame has
been verified as a non-runt)
before receive DMA is request-
ed. Note however that, if the net-
work interface is operating in
half-duplex mode, in order for
receive DMA to be performed for
a new frame, at least 64 bytes
must have been received. This
effectively avoids having to react
to receive frames which are
runts or suffer a collision during
the slot time (512 bit times). If
the Runt Packet Accept feature
is enabled, receive DMA will be
requested as soon as either the
RCVFW threshold is reached, or
a complete valid receive frame is
detected (regardless of length).
RCVFW is set to a value of 10b
(64 bytes) after RESET.
Read/write
accessible
when STOP or SPND bits are
set.
13-12RCVFW[1:0]
Watermark.
only
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相關代理商/技術參數(shù)
參數(shù)描述
AM79C961AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C961KC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C961KC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA
AM79C965A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller
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