參數(shù)資料
型號： AM79C961AVIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 124/206頁
文件大?。?/td> 1507K
代理商： AM79C961AVIW
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124
Am79C961A
9
STP
START OF PACKET indicates
that this is the first buffer to be
used by the PCnet-ISA II con-
troller for this frame. It is used for
data chaining buffers. The STP
bit must be set in the first buffer
of the frame, or the PCnet-ISA II
controller will skip over the
descriptor and poll the next
descriptor(s) until the OWN and
STP bits are set.
STP is written by the host and is
not changed by the PCnet-ISA II
controller.
END OF PACKET indicates that
this is the last buffer to be used
by the PCnet-ISA II
controller for
this frame. It is used for data
chaining buffers. If both STP and
ENP are set, the frame fits into
one buffer and there is no data
chaining. ENP is written by the
host and is not changed by the
PCnet-ISA II controller.
The HIGH ORDER 8 address
bits of the buffer pointed to by
this descriptor. This field is writ-
ten by the host and is not
changed by the PCnet-ISA II
controller.
8
ENP
7-0
HADR
TMD2
Bit
Name
Description
15-12 ONES
MUST BE ONES. This field is
written
by
the
unchanged by the PCnet-ISA II
controller.
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two
’
s complement of the length
of the buffer. This is the number
of bytes from this buffer that will
be transmitted by the PCnet-ISA
II controller. This field is written
by the host and is not changed
by the PCnet-ISA II controller.
There are no minimum buffer
size restrictions. Zero length
buffers are allowed for protocols
which require it.
host
and
11-0
BCNT
TMD3
Bit
Name
Description
15
BUFF
BUFFER ERROR is set by the
PCnet-ISA II controller during
transmission when the PC-
net-ISA II controller does not find
the ENP flag in the current buffer
and does not own the next buff-
er. This can occur in either of two
ways:
1)
The OWN bit of the next
buffer is zero.
2) FIFO underflow occurred
before the PCnet-ISA II
controller obtained the
next STATUS byte
(TMD1[15:8]).
BUFF error will turn off the
transmitter (CSR0, TXON = 0),
if DXSUFLO = 0 (bit 6 CSR3). If
a Buffer Error occurs, an
Underflow Error will also occur.
BUFF is not valid when LCOL
or RTRY error is set during
transmit data chaining. BUFF
is written by the PCnet-ISA II
controller.
UNDERFLOW ERROR indi-
cates that the transmitter has
truncated a message due to
data late from memory. UFLO
indicates that the FIFO has emp-
tied before the end of the frame
was reached. Upon UFLO error,
the transmitter is turned off
(CSR0, TXON = 0), if DXSUFLO
= 0 (bit 6 CSR3). UFLO is written
by the PCnet-ISA II controller.
RESERVED bit. The PCnet-ISA
II controller will write this bit with
a
“
0".
LATE COLLISION indicates that
a collision has occurred after the
slot time of the channel has
elapsed. The PCnet-ISA II con-
troller does not re-try on late col-
lisions. LCOL is written by the
PCnet-ISA II controller.
LOSS OF CARRIER is set in
AUI mode when the carrier is
lost during an PCnet-ISA II con-
troller- initiated transmission.
The PCnet-ISA II controller does
not stop transmission upon loss
of carrier. It will continue to
transmit the whole frame until
done. LCAR is written by the
PCnet-ISA II controller.
In 10BASE-T mode, LCAR will
be set when the T-MAU is in link
fail state.
RETRY ERROR indicates that
the transmitter has failed after
16 attempts to successfully
transmit a message, due to
repeated
collisions
14
UFLO
13
RES
12
LCOL
11
LCAR
10
RTRY
on
the
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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