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參數(shù)資料
| 型號(hào)： | AM79C961AVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 90/206頁(yè) |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AVIW |
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Am79C961A
reads and writes to adjacent ascending addresses in
the SRAM to be performed without intervening writes to
the SRAM Address Pointer. Since buffer accesses
comprise a high percentage of all accesses to the
SRAM, and buffer accesses are typically performed in
adjacent ascending order, the auto-increment of the
SRAM Address Pointer reduces the required ISA bus
cycles significantly.
In addition to the auto-incrementing of the SRAM
Address pointer, the PCnet-ISA II performs write post-
ing on writes to the SRAM and read prefetching on
reads from the SRAM to maximize performance in the
Programmed I/O architecture mode.
Write Posting: When a write cycle to the SRAM Data
Port occurs, the PCnet-ISA II controller stores the data
into an internal holding register, allowing the ISA bus
cycle to finish normally. The data in the holding register
will then be written to the SRAM without the need for
ISA bus control. In the event that the holding register is
already filled with unwritten SRAM data, the PCnet-ISA
II controller will extend the ISA write cycle by driving
OCHRDY LOW until the unwritten data is stored in the
SRAM. Once the data is written into the SRAM, the
new write data is stored into the internal holding regis-
ter and IOCHRDY is released allowing the ISA bus
cycle to complete.
Read Prefetching: To gain performance on read
accesses to the SRAM, the PCnet-ISA II performs
prefetches of the SRAM after every read from the
SRAM Data Port. The prefetch is performed using the
speculated address that results from the auto-incre-
ment that occurs on the SRAM Address Pointer follow-
ing every access to the SRAM Data Port. Following
every read access, the 16-bit word following the
just-read SRAM byte or word is prefetched and placed
in a holding register. If a
word
read from the SRAM
Data Port occurs before a
“
prefetch invalidation event
”
occurs, the prefetched word is driven onto the SD[15:0]
pins without a wait state (no IOCHRDY LOW asser-
tion). A
“
prefetch invalidation event
”
is defined as any
activity on the Private Bus other than SRAM reads.
This includes SRAM writes by either the ISA bus or the
network interface, address or boot PROM reads, or any
write to the SRAM Address Pointer.
The PCnet-ISA II interface to the SRAM in the Pro-
grammed I/O architecture mode is identical to that in
the Shared Memory Architecture mode. Hence, the
SRAM Read and Write cycle descriptions and dia-
grams shown in the
“
Static RAM Cycles
–
Shared
Memory Architecture
”
section apply.
Transmit Operation
The transmit operation and features of the PCnet-ISA
II controller are controlled by programmable options.
Transmit Function Programming
Automatic transmit features, such as retry on collision,
FCS generation/transmission, and pad field insertion,
can all be programmed to provide flexibility in the
(re-)transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initializa-
tion block.
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4. If APAD_XMT is set, auto-
matic pad field insertion is enabled, the DXMTFCS fea-
ture is over-ridden, and the 4-byte FCS will be added to
the transmitted frame unconditionally. If APAD_XMT is
cleared, no pad field insertion will take place and runt
packet transmission is possible.
The disable FCS generation/transmission feature can
be programmed dynamically on a frame by frame
basis. See the ADD_FCS description of TMD1.
Transmit FIFO Watermark (XMTFW in CSR80) sets
the point at which the BMU (Buffer Management Unit)
requests more data from the transmit buffers for the
FIFO. This point is based upon how many 16-bit bus
transfers (2 bytes) could be performed to the existing
empty space in the transmit FIFO.
Transmit Start Point (XMTSP in CSR80) sets the point
when the transmitter actually tries to go out on the
media. This point is based upon the number of bytes
written to the transmit FIFO for the current frame.
When the entire frame is in the FIFO, attempts at trans-
mission of preamble will commence regardless of the
value in XMTSP. The default value of XMTSP is 10b,
meaning 64 bytes full.
Automatic Pad Generation
Transmit frames can be automatically padded to ex-
tend them to 64 data bytes (excluding preamble). This
allows the minimum frame size of 64 bytes (512 bits)
for 802.3/Ethernet to be guaranteed with no software
intervention from the host/controlling process. Setting
the APAD_XMT bit in CSR4 enables the automatic
padding feature. The pad is placed between the LLC
data field and FCS field in the 802.3 frame. FCS is al-
ways added if the frame is padded, regardless of the
state of DXMTFCS. The transmit frame will be padded
by bytes with the value of 00h. The default value of
APAD_XMT is 0, and this will disable auto pad genera-
tion after RESET.
It is the responsibility of upper layer software to cor-
rectly define the actual length field contained in the
message to correspond to the total number of LLC
Data bytes encapsulated in the packet (length field as
defined in the IEEE 802.3 standard). The length value
contained in the message is not used by the PCnet-ISA
II controller to compute the actual number of pad bytes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C965A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
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