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參數(shù)資料
| 型號： | AM79C961AVIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 45/206頁 |
| 文件大小： | 1507K |
| 代理商： | AM79C961AVIW |
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Am79C961A
45
FUNCTIONAL DESCRIPTION
The PCnet-ISA II controller is a highly integrated system
solution for the PC-AT ISA architecture. It provides a Full
Duplex Ethernet controller, AUI port, and 10BASE-T
transceiver. The PCnet-ISA II controller can be directly in-
terfaced to an ISA system bus. The PCnet-ISA II control-
ler contains an ISA bus interface unit, DMA Buffer
Management Unit, 802.3 Media Access Control function,
separate 136-byte transmit and 128-byte receive FIFOs,
IEEE defined Attachment Unit Interface (AUI), and
Twisted-Pair Transceiver Media Attachment Unit. In addi-
tion, a Sleep function has been incorporated which pro-
vides low standby current for power sensitive applications.
The PCnet-ISA II controller is register compatible with
the LANCE (Am7990) Ethernet controller and PC-
net-ISA (Am79C960). The DMA Buffer Management
Unit supports the LANCE descriptor software model
and the PCnet-ISA II controller is software compatible
with the Novell NE2100 and NE1500T add-in cards.
External remote boot PROMs and Ethernet physical
address PROMs are supported. The location of the I/O
registers, Ethernet address PROM, and the boot PROM
are determined by the programming of the registers in-
ternal to PCnet-ISA II. These registers are loaded at
RESET from the EEPROM, if an EEPROM is utilized.
Normally, the Ethernet physical address will be stored in
the EEPROM with the other configuration data. This
reduces the parts count, board space requirements,
and power consumption. The option to use a standard
parallel 8 bit PROM is provided to manufactures who
are concerned about the non-volatile nature of
EEPROMs.
The PCnet-ISA II controller
’
s bus master architecture
brings to system manufacturers (adapter card and
motherboard makers alike) something they have not
been able to enjoy with other architectures
—
a low-cost
system solution that provides the lowest parts count
and highest performance. As a bus-mastering device,
costly and power-hungry external SRAMs are not
needed for packet buffering. This results in lower sys-
tem cost due to fewer components, less real-estate and
less power. The PCnet-ISA II controller
’
s advanced bus
mastering architecture also provides high data through-
put and low CPU utilization for even better performance.
To offer greater flexibility, the PCnet-ISA II controller has
a Bus Slave mode to meet varying application needs.
The bus slave mode utilizes a local SRAM memory to
store the descriptors and buffers that are located in sys-
tem memory when in Bus Master mode. The SRAM can
be slave accessed on the ISA bus through memory
cycles in Shared Memory mode or I/O cycles in Pro-
grammed I/O mode. The Shared Memory and Pro-
grammed I/O architectures offer maximum compatibility
with low-end machines, such as PC/XTs that do not
support bus mastering, and very high end machines
which require local packet buffering for increased
system latency.
The network interface provides an Attachment Unit
Interface and Twisted-Pair Transceiver functions. Only
one interface is active at any particular time. The AUI
allows for connection via isolation transformer to
10BASE5 and 10BASE2, thick and thin based coaxial
cables. The Twisted-Pair Transceiver interface allows
for connection of unshielded twisted-pair cables as
specified by the Section 14 supplement to IEEE 802.3
Standard (Type 10BASE-T).
Important Note About The EEPROM
Byte Map
The user is cautioned that while the Am79C961A (PC-
net-ISA II) and its associated EEPROM are pin compatible
to their predecessors the Am79C961 (PCnet-ISA
+
) and its
associated EEPROM, the byte map structure in each of
the EEPROMs are different from each other.
The EEPROM byte map structure used for the
Am79C961A PCnet-ISA II has the addition of
“
MISC Con-
fig 2, ISACSR9" at word location 10Hex. The EEPROM
byte map structure used for the Am79C961 PCnet-ISA+
does not have this.
Therefore, should the user intend to replace the PC-
net-ISA
+
with the PCnet-ISA II, care
MUST
be taken to re-
program the EEPROM to reflect the new byte map
structure needed and used by the PCnet-ISA II. For addi-
tional information, refer to the section in this data sheet
under
EEPROM
and the Am79C961 PCnet-ISA
+
data
sheet (PID #18183) under the sections entitled
EEPROM
and
Serial EEPROM Byte Map
.
Bus Master Mode
System Interface
The PCnet-ISA II controller has two fundamental oper-
ating modes, Bus Master and Bus Slave. Within the Bus
Slave mode, the PCnet-ISA II can be programmed for a
Shared Memory or Programmed I/O architecture. The
selection of either the Bus Master mode or the Bus
Slave mode must be done through hard wiring; it is not
software configurable. When in the Bus Slave mode, the
selection of the Shared Memory or Programmed I/O
architecture is done through software with the PIOSEL
bit (ISACSR2, bit 13).
The optional Boot PROM is in memory address space
and is expected to be 8
–
64K. On-chip address compar-
ators control device selection is based on the value in
the EEPROM.
The address PROM, board configuration registers, and
the Ethernet controller occupy 24 bytes of I/O space
and can be located at 16 different starting addresses.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961KC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C965A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
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