
P R E L I M I N A R Y
AMD
53
Am53C94/Am53C96
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
t
PD
t
PWL
t
S
t
S
t
P
t
PD
t
PWH
t
PWL
t
H
t
P
t
PD
t
Z
t
H
t
PD
t
PWH
t
S
t
S
t
P
t
PWH
t
PWL
t
H
t
P
t
PD
t
H
t
S
DACK
to DREQ Valid Delay
DACK
Pulse Width Low
BHE, AS0 to
DMARD
Set Up Time
DACK
to
DMARD
Set Up Time
DMARD
to
DMARD
period
DMARD
to Data Valid Delay
DMARD
Pulse Width High
DMARD
Pulse Width Low
BHE, AS0 to
DMARD
Hold Time
DMARD
to
DMARD
period
DMARD
to DREQ Valid Delay
DMARD
to Data High Impedance
DMARD
to Data Hold Time
DACK
to DREQ Valid Delay
DACK
Pulse Width High
DACK
to
DMAWR
Set Up Time
BHE, AS0 to
DMAWR
Set Up Time
DMAWR
to
DMAWR
period
DMAWR
Pulse Width High
DMAWR
Pulse Width Low
BHE, AS0 to
DMAWR
Hold Time
DMAWR
to
DMAWR
period
DMAWR
to DREQ Valid Delay
Data to
DMAWR
Hold Time
Data to
DMAWR
Set Up Time
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
20
0
130
70
60
70
20
t
3 +
50
140
50
2
50
60
0
20
160
60
100
20
t
3 +
50
140
0
15
Parameter
Symbol
No.
Parameter Description
Test Conditions
Min
Max
Unit
Note:
There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B).