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參數(shù)資料
| 型號： | AM53C96KCW |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High Performance SCSI Controller |
| 中文描述： | 高性能SCSI控制器 |
| 文件頁數(shù)： | 32/63頁 |
| 文件大?。?/td> | 455K |
| 代理商： | AM53C96KCW |
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P R E L I M I N A R Y
AMD
32
Am53C94/Am53C96
CNTLREG3 – Bit 0 – BS8 – Burst Size 8
The BS8 bit is used to modify the timing of the DREQ
signal with respect to the
DMARD
and
DMAWR
signals.
The BS8 bit is used in conjunction with the Modify DMA
Mode (MDM) bit in the CNTLREG3. Both bits have to be
set for proper operation.
When the BS8 bit is set the device delays the assertion
of the DREQ signal until 8 bytes or 4 words transfer is
possible.
When the BS8 bit is set and the device is in a DMA write
mode the DREQ signal will be asserted only when 8 byte
locations are available for writing. In the DMA read
mode the DREQ signal will go active under the following
circumstances:
At the end of a transfer,
I
In the target mode,
– when the transfer is complete
or
– when the
ATN
signal is active
In the initiator mode,
– when the Current Transfer Register
is decremented to zero
or
– after any phase change
I
In the middle of a transfer
I
In the initiator mode,
– when the last 8 bytes of the FIFO are full
– during Synchronous Data-In transfer when the
Event Transfer Count Register is greater than
7 and the last 8 bytes of the FIFO are full.
When the BS8 bit is reset and the device is in a DMA
read or write mode the DREQ signal will toggle every
time the data is strobed by the
DMARD
or
DMAWR
signals.
Using Bit 0 (BS8) and Bit 1 (MDM) of Control
Register 3, one can enable the different combination
modes shown in the table below.
Maximum
Synchronous
Offset
15
7
–
15
(MDM) (BS8)
Bit 1
0
0
1
1
Function
Bit 0
0
1
0
1
Normal DMA Mode
Burst Size 8 Mode
Reserved
Modified DMA Mode
Data Alignment Register (0FH) Write
16506C-33
The Data Alignment Register (DALREG) is used if the
first byte of a 16-bit DMA transfer from the SCSI bus to
the host processor is misaligned. Prior to issuing an in-
formation transfer command, the host processor must
set the Data Alignment Enable (DAE) bit in the
CNTLREG2.
DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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