參數(shù)資料
型號： AM53C96KCW
廠商： Advanced Micro Devices, Inc.
英文描述： High Performance SCSI Controller
中文描述： 高性能SCSI控制器
文件頁數(shù)： 17/63頁
文件大小： 455K
代理商： AM53C96KCW
P R E L I M I N A R Y
AMD
17
Am53C94/Am53C96
Current Transfer Count Register
(00H–01H) Read Only
Current Transfer Count Register
CTCREG
Address: 00
H–
01
H
Type: Read
15
14
13
12
11
10
9
8
CRVL15 CRVL14
CRVL13
CRVL12 CRVL11 CRVL10
CRVL9
CRVL8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
CRVL7
CRVL6
CRVL5
CRVL4
CRVL3
CRVL2
CRVL1
CRVL0
x
x
x
x
x
x
x
x
16506C-16
CTCREG – Bits 15:0 – CRVL 15:0 – Current
Value 15:0
This is a two-byte register. It counts down to keep track
of the number of DMA transfers. Reading this registers
will return the current value of the counter. The counter
will decrement by one for every byte transferred and two
for every word transferred over the SCSI bus. The trans-
action is complete when the count reaches zero. These
registers are automatically loaded with the values in the
Start Transfer Count Register every time a DMA com-
mand is issued.
In the target mode, this counter is decremented by the
active edge of
DACK
during the Data-In phase and by
REQC
during the Data-Out phase.
In the initiator mode, the counter is decremented by the
active edge of
DACK
during the Synchronous Data-In
phase or by
ACKC
during the Asynchronous Data-In
phase and by
DACK
during the Data-Out phase.
Start Transfer Count Register (00H–01H)
Write Only
Start Transfer Count Register
STCREG
Address: 00
H–
01
H
Type: Write
15
14
13
12
11
10
9
8
STVL15
STVL14
STVL13
STVL12
STVL11
STVL10
STVL9
STVL8
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
STVL7
STVL6
STVL5
STVL4
STVL3
STVL2
STVL1
STVL0
x
x
x
x
x
x
x
x
16506C-017
STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0
This is a two-byte register. It contains the number of
bytes to be transferred during a DMA operation. The
value of this register is set to the number of bytes to be
transferred prior to a DMA transfer command. This reg-
ister retains its programmed value until it is overwritten
and is not affected by hardware or software reset.
Therefore, it is not necessary to reprogram the count for
subsequent DMA transfers of the same size. Writing a
zero to this register sets a maximum transfer count of
65536 bytes. The value in this register is undefined at
power-up.
FIFO Register (02H) Read/Write
FIFO Register
FFREG
7
Address: 02
H
Type: Read/Write
1
6
5
4
3
2
0
FF7
FF6
FF5
FF4
FF3
FF2
FF1
FF0
0
0
0
0
0
0
0
0
16506C-18
FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0
The bottom of the 16x9 FIFO is mapped into the FIFO
Register address. By reading and writing this register
the bottom of the FIFO can be read or written. This is the
only register that can also be accessed by
DACK
along
with
DMARD
or
DMAWR
. This register is reset to zero
by hardware or software reset and also at the start of a
selection or reselection sequence.
Command Register (03H) Read/Write
Command Register
CMDREG
Address: 03
H
Type: Read/Write
7
6
5
4
3
2
1
0
DMA
CMD6
CMD5
CMD4
CMD3
CMD2
CMD1
CMD0
x
x
x
x
x
x
x
x
Command 6:0
Direct Memory
Access
16506C-019
Commands to the device are issued by writing to this
register. This register is two deep which allows for com-
mand queuing. The second command can be issued be-
fore the first one is completed. The Reset command and
the Stop DMA command are not queued and are exe-
cuted immediately. Reading this register will return the
command currently being executed (or the last com-
mand executed if there are no pending commands).
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