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參數(shù)資料
| 型號： | AM53C96KCW |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High Performance SCSI Controller |
| 中文描述： | 高性能SCSI控制器 |
| 文件頁數(shù)： | 21/63頁 |
| 文件大?。?/td> | 455K |
| 代理商： | AM53C96KCW |
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P R E L I M I N A R Y
AMD
21
Am53C94/Am53C96
Interrupt Status Register (05H) Read
SRST
ICMD
DIS
SR
SO
0
0
0
0
0
Interrupt Status Register
INSTREG
Address: 05h
Type: READ
7
6
5
4
3
2
1
0
RESEL
SELA
SEL
0
0
0
Invalid Command
SCSI Reset
Disconnected
Service Request
Successful Operation
Selected with Attention
Reselected
16506C-22
Selected
The Interrupt Status Register (INSTREG) will indicate
the reason for the interrupt. This register is used with the
Status Register (STATREG) and Internal Status Regis-
ter (ISREG) to determine the reason for the interrupt.
Reading the INSTREG will clear all three registers.
INSTREG – Bit 7 – SRST – SCSI Reset
The SRST bit will be set if a SCSI Reset is detected and
SCSI reset reporting is enabled via the DISR (bit 6) of
the CNTLREG1.
INSTREG – Bit 6 – ICMD – Invalid Command
The ICMD bit will be set if the device detects an illegal
command code. This bit is also set if a command code
from a different mode is detected than the mode the de-
vice is currently in.
INSTREG – Bit 5 – DIS – Disconnected
The DIS bit can be set in the target or the initiator mode
when the device disconnects from the SCSI bus. In the
target mode this bit will be set if a terminate or a com-
mand complete sequence causes the device to discon-
nect from the SCSI bus. In the Initiator mode this bit will
be set if the target disconnects or a selection or reselec-
tion timeout occurs.
INSTREG – Bit 4 – SR – Service Request
The SR bit can be set in the target or the initiator mode
when another device on the SCSI bus has a service re-
quest. In the target mode this bit will be set when the in-
itiator asserts the
ATN
signal. In the Initiator mode this
bit is set whenever the target requests an information
transfer phase.
INSTREG – Bit 3 – SO – Successful Operation
The SO bit can be set in the target or the initiator mode
when an operation is successfully complete. In the
target mode this bit will be set when any target mode
command is completed. In the initiator mode this bit is
set after a target has been successfully selected, after a
command is successfully completed and after an infor-
mation transfer command when the target requests a
message in phase.
INSTREG – Bit 2 – RESEL – Reselected
The RESEL bit is set at the end of the reselection phase
indicating that the device has been reselected as an in-
itiator.
INSTREG – Bit 1 – SELA – Selected with Attention
The SELA bit is set at the end of the selection phase indi-
cating that the device has been selected and that the
ATN
signal was active during the selection.
INSTREG – Bit 0 – SEL – Selected
The SEL bit is set at the end of the selection phase indi-
cating that the device has been selected and that the
ATN
signal was inactive during the selection.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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