參數(shù)資料
型號(hào): AM53C96KCW
廠商: Advanced Micro Devices, Inc.
英文描述: High Performance SCSI Controller
中文描述: 高性能SCSI控制器
文件頁(yè)數(shù): 27/63頁(yè)
文件大小: 455K
代理商: AM53C96KCW
P R E L I M I N A R Y
AMD
27
Am53C94/Am53C96
Current FIFO/Internal State Register (07H) Read
Current FIFO/Internal State Register
CFISREG
Address: 07
H
Type: Read
7
6
5
4
3
2
1
0
IS2
IS1
IS0
CF4
CF3
CF2
CF1
CF0
0
0
0
0
0
0
0
0
Internal State 2:0
Current FIFO 4:0
16506C-26
This register has two fields, the Current FIFO field and
the Internal State field.
CFISREG – Bits 7:5 – IS 2:0 – Internal State 2:0
The Internal State Register (ISREG) tracks the progress
of a sequence-type command.
The IS 2:0 bits are duplicated from the IS 2:0 field in the
Internal State Register (ISREG) in the normal mode. If
the device is in the test mode, IS 0 is set to indicate that
the offset value is non zero. A non zero value indicates
that synchronous data transfer can continue. A zero
value indicates that the synchronous offset count has
been reached and no more data can be transferred until
an acknowledge is received.
CFISREG – Bits 4:0 – CF 4:0 – Current FIFO 4:0
The CF 4:0 bits are the binary coded value of the num-
ber of bytes in the FIFO. These bits should not be read
when the device is transferring data since this count
may not be stable.
Synchronous Offset Register (07H) Write
Synchronous Offset Register
SOFREG
Address: 07
H
Type: Write
7
6
5
4
3
2
1
0
SO3
SO2
SO1
SO0
RES
RES
RES
RES
x
x
x
x
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Synchronous Offset 3:0
16506C-27
The Synchronous Offset Register (SOFREG) contains
a 4-bit count of the number of bytes that can be sent to
(or received from) the SCSI bus without an
ACK
(or
REQ
). Bytes exceeding the threshold will be sent one
byte at a time (asynchronously). That is, each byte will
require an
ACK
/
REQ
handshake. To set up an asyn-
chronous transfer, the SOFREG is set to zero. The
SOFREG is set to zero after a hard or soft reset.
SOFREG – Bits 7:4 – RES – Reserved
SOFREG – Bits 3:0 – SO 3:0 – Synchronous Offset
3:0
The SO 4:0 bits are the binary coded value of the num-
ber of bytes that can be sent to (or received from) the
SCSI bus without an
ACK
(or
REQ
) signal.
相關(guān)PDF資料
PDF描述
AM53C94 Intergrated Optical Disk Controller
AM80C186 Circular Connector; No. of Contacts:3; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:12-3 RoHS Compliant: No
AM80C286 Circular Connector; No. of Contacts:10; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No
AM53C96 Intergrated Optical Disk Controller
AM95C98 Intergrated Optical Disk Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM53C974KC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller
AM53CF94 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced SCSI-2 Controller (ESC)
AM53CF94/AM53CF96 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am53CF94/Am53CF96 ? 572KB (PDF) Enhanced SCSI-2 Controller (ESC)?
AM53CF94JC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced SCSI-2 Controller (ESC)
AM53CF94JCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced SCSI-2 Controller (ESC)