參數(shù)資料
型號(hào)： AM53C96KCW
廠商： Advanced Micro Devices, Inc.
英文描述： High Performance SCSI Controller
中文描述： 高性能SCSI控制器
文件頁(yè)數(shù)： 31/63頁(yè)
文件大?。?/td> 455K
代理商： AM53C96KCW
P R E L I M I N A R Y
AMD
31
Am53C94/Am53C96
Group 2 Command Recognition: When the S2FE bit is
set the group 2 commands are recognized as 10 byte
commands. The GCV (Group Code Valid) bit in the
STATREG (04H) is set. When the S2FE bit is reset, the
device will interpret the group 2 commands as reserved
commands and will request 6 byte commands. The
GCV bit in the STATREG will not be set in this case.
CNTLREG2 – Bit 2 – ACDPE – Abort on Command/
Data Parity Error
The ACDPE bit when set allows the device to abort a
command or data transfer when a parity error is de-
tected. When the ACDPE bit is reset parity error is ig-
nored.
CNTLREG2 – Bit 1 – PGRP – Pass Through/Gener-
ate Register Parity
The PGRP bit when set causes the data along with the
parity from the host to pass through to the FIFO under
the control of the
CS
and the
WR
signals. When the
PGRP bit is reset, the device generates the parity on the
data from the host before writing it to the FIFO.
When the device is placing the data on the SCSI bus, it
will check for an outgoing parity error if either the PGRP
bit is set or the PGDP (Pass Through/Generate Data
Parity) bit is set.
CNTLREG2 – Bit 0 – PGDP – Pass Through/Gener-
ate Data Parity
The PGDP bit when set causes the data along with the
parity from the host to pass through to the FIFO under
the control of the
DACK
and the
WR
signals. When the
PGDP bit is reset, the device generates the parity on the
data from the host before writing it to the FIFO.
When the device is placing the data on the SCSI bus, it
will check for an outgoing parity error if either the PGDP
bit is set or the PGRP (Pass Through/Generate Register
Parity) bit is set.
4
Control Register Three
CNTLREG3
Address: 0C
H
Type: Read/Write
7
6
5
3
2
1
0
RES
RES
RES
RES
RES
LBTM
MDM
BS8
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Last Byte Transfer Mode
Modify DMA Mode
Burst Size 8
16506C-32
Control Register Three (0CH) Read/Write
CNTLREG3 – Bits 7:3 – RES – Reserved
CNTLREG3 – Bit 2 – LBTM – Last Byte Transfer
Mode
The LBTM bit specifies how the last byte in an odd byte
transfer is handled during 16-bit DMA transfers. This
mode is not used if byte control is selected via BUSMD
1:0 inputs and BSO (Byte Select Order) bit in the
CNTLREG2. This mode has no affect during 8-bit DMA
transfers and on transfers on the SCSI bus.
When the LBTM bit is set the DREQ signal will not be
asserted for the last byte, instead the host will read or
write the last byte from or to the FIFO. When the LBTM
bit is reset the DREQ signal will be asserted for the last
byte and the following 16-bit DMA transfer will contain
the last byte on the lower bus. If the transfer is a DMA
read the upper bus will be all ones.
The LBTM bit is reset by hard or soft reset.
CNTLREG3 – Bit 1 – MDM – Modify DMA Mode
The MDM bit is used to modify the timing of the
DACK
signal with respect to the
DMARD
and
DMAWR
signals.
The MDM bit is used in conjunction with the Burst Size 8
(BS8) bit in the CNTLREG3. Both bits have to be set for
proper operation.
When the MDM bit is set and the device is in a DMA read
or write mode the
DACK
signal will remain asserted
while the data is strobed by the
DMARD
or
DMAWR
sig-
nals. In the DMA read mode when BUSMD 1:0 = 11 the
DACK
signal will toggle for every DMA read.
When the MDM bit is reset and the device is in a DMA
read or write mode the
DACK
signal will toggle every
time the data is strobed by the
DMARD
or
DMAWR
signals.
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