參數(shù)資料
型號： AM53C96KCW
廠商： Advanced Micro Devices, Inc.
英文描述： High Performance SCSI Controller
中文描述： 高性能SCSI控制器
文件頁數(shù)： 16/63頁
文件大?。?/td> 455K
代理商： AM53C96KCW
P R E L I M I N A R Y
AMD
16
Am53C94/Am53C96
SELC
Select Control
(Output, Active Low, Open Drain)
This is a SCSI output with 48 mA drive. When the device
is configured in the Single Ended SCSI Mode (
DFMODE
inactive) this pin is defined as a
SEL
output for the SCSI
bus. When the device is configured in the Differential
SCSI Mode (
DFMODE
active) this pin is defined as the
direction control for the external differential transceiver.
In this mode, a signal high state corresponds to an out-
put to the SCSI bus and a low state corresponds to an
input from the SCSI bus.
RSTC
Reset Control
(Output, Active Low, Open Drain)
This is a SCSI output with 48 mA drive. The Reset SCSI
command will cause the device to drive
RSTC
active for
25 ms–40 ms, which will depend on the CLK frequency
and the conversion factor. When the device is config-
ured in the Single Ended SCSI Mode (
DFMODE
inac-
tive) this pin is defined as a RST output for the SCSI bus.
When the device is configured in the Differential SCSI
Mode (
DFMODE
active) this pin is defined as the direc-
tion control for the external differential transceiver. In
this mode, a signal high state corresponds to an output
to the SCSI bus and a low state corresponds to an input
from the SCSI bus.
REQC
Request Control
(Output, Active Low, Open Drain)
This is a SCSI output with 48 mA drive. This signal is ac-
tivated only in the target mode.
ACKC
Acknowledge Control
(Output, Active Low, Open Drain)
This is a SCSI output with 48 mA drive. This signal is ac-
tivated only in the initiator mode.
ISEL
Initiator Select
(Output, Active High)
This signal is available on the Am53C96 only. This sig-
nal is active whenever the device is in the initiator mode.
In the differential mode this signal is used to enable the
initiator signals
ACKC
and
ATN
and the device also
drives these signals.
TSEL
Target Select
(Output, Active High)
This signal is available on the Am53C96 only. This sig-
nal is active whenever the device is in the target mode.
In the differential mode this signal is used to enable the
target signals
REQC
,
MSG
,
C/D
and
I/O
and the device
also drives these signals.
FUNCTIONAL DESCRIPTION
Register Map
Address
(Hex.) Operation
Register
00
Read
Current Transfer Count
Register LSB
Start Transfer Count Register
LSB
Current Transfer Count
Register MSB
Start Transfer Count Register
MSB
FIFO Register
Command Register
Status Register
SCSI Destination ID Register
Interrupt Status Register
SCSI Timeout Register
00
Write
01
Read
01
Write
02
03
04
04
05
05
Read/Write
Read/Write
Read
Write
Read
Write
Address
(Hex.) Operation
Register
06
Read
Internal State Register
06
Write
Synchronous Transfer Period
Register
Current FIFO/Internal State
Register
Synchronous Offset Register
Control Register 1
Clock Factor Register
Forced Test Mode Register
Control Register 2
Control Register 3
07
Read
07
08
09
0A
0B
0C
Write
Read/Write
Write
Write
Read/Write
Read/Write
0F
Write
Data Alignment Register
Note:
Not all registers in this device are both readable and writable. Some read only registers share the same address with write only
registers. The registers can be accessed by asserting the
CS
signal and then asserting either
RD
or
WR
signal depending on the
operation to be performed. Only the FIFO Register can be accessed by asserting either
CS
or
DACK
n conjunction with
RD
and
WR
signals or
DMARD
and
DMAWR
signals. The register address inputs are ignored when
DACK
is used but must be valid
when
CS
is used.
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