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參數(shù)資料
| 型號(hào)： | ADV7322 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit HDTV Video Encoder |
| 中文描述： | 多格式11位高清晰度電視視頻編碼器 |
| 文件頁(yè)數(shù)： | 29/88頁(yè) |
| 文件大?。?/td> | 991K |
| 代理商： | ADV7322 |
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Preliminary Technical Data
ADV7322
Table 10. Register 0x12
SR7–
SR0
Register
0x12
HD Mode
Register
3
Rev. PrA | Page 29 of 88
Bit Description
HD Y Delay with Respect
to Falling Edge of HSYNC
Bit 7
0
1
Bit 6
0
1
Bit 5
0
0
0
0
1
Bit 4
0
0
1
1
0
Bit 3
0
1
0
1
0
Bit 2
0
0
0
0
1
Bit 1
0
0
1
1
0
Bit 0
0
1
0
1
0
Register Setting
0 clk cycles
1 clk cycles
2 clk cycles
3 clk cycles
4 clk cycles
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
4 clk cycles
Disabled
Enabled
Disabled
Enabled
Reset
Values
0x00
HD Color Delay with
Respect to Falling Edge of
HSYNC
HD CGMS
HD CGMS CRC
Table 11. Registers 0x13 to 0x14
SR7–
SR0
Register
0x13
HD Mode
Register 4
Bit Description
HD Cr/Cb Sequence
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Register Setting
Cb after falling edge of HSYNC.
Cr after falling edge of HSYNC.
0 must be written to this bit.
0 must be written here
Disabled.
Enabled.
0 must be written to this bit.
Disabled.
Enabled.
4:4:4
4:2:2
Disabled.
Enabled.
A low-high-low transition
resets the internal HD timing
counters.
Signal duration on S_Hsync
same as ADV731x.
Signal duration on S_Hsync =
sync duration on embedded Y.
Field signal out on S_Vsync pin.
Vsync Signal. Duration = Vsync
on embedded Y.
BLANK active high.
BLANK active low.
Macrovision disabled.
Macrovision enabled.
0 must be written to these bits.
Reset
Values
0x4C
1
Reserved
Reserved
Sinc Filter on DAC D, E, F
0
1
0
1
0
1
0
0
1
0
0
x
0x00
Reserved
HD Chroma SSAF
HD Chroma Input
HD Double Buffering
HD Timing Reset
0
HD Hsync Generation
1
1
0
1
HD Vsync Generation
1
0
HD Blank Polarity
1
0
0
1
HD Macrovision for 525p
and 625p
Reserved
0
1
0 = field input.
1 = VSYNC input.
Update Horizontal/Vertical
counters.
Horizontal/Vertical counters
free running.
HD VSYNC/Field Input
0
0x14
HD Mode
Register 5
Horizontal/Vertical
counters
2
1
1
Used in conjunction with HD_SYNC in Register 0x02, Bit 7 set to 1.
2
When set to 0, the Horizontal/Vertical counters automatically wrap around at the end of the Line/field/frame of the standard selected. When set to 1, the
Horizontal/Vertical counters are free running and wrap around when external sync signals indicate so.
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