參數(shù)資料
型號(hào)： ADV7322
廠商： Analog Devices, Inc.
英文描述： Multiformat 11-Bit HDTV Video Encoder
中文描述： 多格式11位高清晰度電視視頻編碼器
文件頁(yè)數(shù)： 26/88頁(yè)
文件大小： 991K
代理商： ADV7322
ADV7322
Preliminary Technical Data
REGISTER ACCESS
The MPU can write to or read from all of the registers of the
ADV7322 except the subaddress registers, which are write only
registers. The subaddress register determines which register the
next read or write operation will access. All communications
with the part through the bus start with an access to the
subaddress register. A read/write operation is then performed
from/to the target address, which increments to the next
address until a stop command is performed on the bus.
Rev. PrA | Page 26 of 88
REGISTER PROGRAMMING
The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The communication register is an 8-bit write-only register. After
the part is accessed over the bus and a read/write operation is
selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
Table 7. Registers 0x00 to 0x01
SR7–
SR0
0x00
Register
Power
Mode
Register
Bit Description
Sleep Mode. With this
control enabled, the
current consumption is
reduced to μA level. All
DACs and the internal PLL
cct are disabled. I
2
C
registers can be read from
and written to in sleep
mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the oversampling to be
switched off.
DAC F: Power On/Off.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Register Setting
Sleep mode off.
Sleep mode on.
Reg. Reset
Values
(Shaded)
0xFC
0
1
PLL on.
PLL off.
0
1
0
1
0
1
0
1
0
1
0
1
0
DAC F off.
DAC F on.
DAC E off.
DAC E on.
DAC D off.
DAC D on.
DAC D off.
DAC C on.
DAC B off.
DAC B on.
DAC A off.
DAC A on.
Reserved
DAC E: Power On/Off.
DAC D: Power On/Off.
DAC C: Power On/Off.
DAC B: Power On/Off.
DAC A: Power On/Off.
Reserved
0
Cb clocked on rising
edge.
Y clocked on rising edge
Must be set if the phase
delay between the two
input clocks is
<9.25 ns or >27.75 ns.
SD input only.
PS input only.
HDTV input only.
SD and PS [16-bit].
SD and PS [8-bit].
SD and HDTV [SD
oversampled].
SD and HDTV [HDTV
oversampled].
PS only [at 54 MHz].
Allows data to be
applied to data ports in
various configurations
(SD feature only).
Clock Edge.
0
1
0
1
Only for PS
interleaved
input at 27 MHz.
Only if two
input clocks are
used.
Reserved.
Clock Align.
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0x38
1
1
0
Input Mode.
0
1
1
1
0x01
Mode
Select
Register
Y/C/S Bus Swap.
1
See Table 21.
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