- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294846 > ADV7152 (Analog Devices, Inc.) CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | ADV7152 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器) |
| 中文描述： | 220兆赫的CMOS真彩色圖形三路10位顯存，數(shù)模轉(zhuǎn)換器（三通道，10位視頻RAM的的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 322K |
| 代理商： | ADV7152 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁
ADV7152
–8–
REV. B
PIN FUNCTION DESCRIPTION
Mnemonic
Function
RED (R0A . . . R0B–R7A . . . R7B),
Pixel Port (TTL Compatible Inputs). 48 pixel select inputs, with 8 bits each for Red, 8
GREEN (G0A . . . G0B–G7A. . . G7B),
bits for Green and 8 bits for Blue. Each bit is multiplexed [A-B] 2:1 or 1:1. It can be
BLUE (B0A . . . B0B–B7A . . . B7B)
configured for 24-Bit True-Color Data, 8-Bit Pseudo-Color Data and 15-Bit True-Color
Data formats. Pixel Data is latched into the device on the rising edge of LOADIN.
PS0A . . . PS0B, PS1A . . . PS1B
Palette Priority Selects (TTL Compatible Inputs): These pixel port select inputs deter-
mine whether or not the device’s pixel data port is selected on a pixel by pixel basis. The
palette selects allow switching between multiple palette devices. The device can be pre-
programmed to completely shut off the DAC analog outputs. If the values of PS0 and
PS1 match the values programmed into bits MR16 and MR17 of the Mode Register,
then the device is selected. Each bit is multiplexed [A-B] 2:1 or 1:1. PS0 and PS1 are
latched into the device on the rising edge of LOADIN.
LOADIN
Pixel Data Load Input (TTL Compatible Input). This input latches the multiplexed
pixel data, including PS0–PS1,
BLANK and SYNC into the device.
LOADOUT
Pixel Data Load Output (TTL Compatible Output). This output control signal runs at a
divided down frequency of the pixel CLOCK input. Its frequency is a function of the
multiplex rate. It can be used to directly or indirectly drive LOADIN
fLOADOUT = fCLOCK/M
where (M = 1 for 1:1 Multiplex Mode)
where (M = 2 for 2:1 Multiplex Mode).
PRGCKOUT
Programmable Clock Output (TTL Compatible Output). This output control signal
runs at a divided down frequency of the pixel CLOCK input. Its frequency is user
programmable and is determined by bits CR30 and CR31 of Command Register 3
fPRGCKOUT = fCLOCK/N
where N = 4, 8, 16 and 32.
SCKIN
Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally
gated synchronously with the
BLANK signal. The resultant output, SCKOUT, is a
video clocking signal that is stopped during video blanking periods.
SCKOUT
Video Shift Clock Output (TTL Compatible Output). This output is a synchronously
gated version of SCKIN and
BLANK. SCKOUT, is a video clocking signal that is
stopped during video blanking periods.
CLOCK,
CLOCK
Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to
be driven by ECL logic levels configured for single supply (+5 V) operation. The clock
rate is normally the pixel clock rate of the system.
BLANK
Composite Blank (TTL Compatible Input). This video control signal drives the analog
outputs to the blanking level.
SYNC
Composite-Sync Input (TTL Compatible Input). This video control signal drives the
IOG analog output to the
SYNC level. It is only asserted during the blanking period.
CR22 in Command Register 2 must be set if
SYNC is to be decoded onto the analog
output, otherwise the
SYNC input is ignored.
SYNCOUT
Composite SYNC O/P (TTL Compatible Output). This video output is a delayed ver-
sion of
SYNC. The delay corresponds to the number of pipeline stages of the device.
D0–D9
Databus (TTL Compatible Input/Output Bus). Data, including color palette values and
device control information is written to and read from the device over this 10-bit, bidi-
rectional databus. 10-bit data or 8-bit data can be used. The databus can be configured
for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any un-
used bits of the databus should be terminated through a resistor to either digital power
plane (VCC) or GND.
CE
Chip Enable (TTL Compatible Input). This input must be at Logic “0” when writing to
or reading from the device over the databus (D0–D9). Internally, data is latched on the
rising edge of
CE.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AE101SD1CQ | TOGGLE SWITCH, SPDT, LATCHED, 2A, 30VDC, THROUGH HOLE-STRAIGHT |
| AE105E11A35SD | 13 CONTACT(S), ALUMINUM ALLOY, FEMALE, MIL SERIES CONNECTOR, CRIMP, RECEPTACLE |
| AE105E11A35S | 13 CONTACT(S), ALUMINUM ALLOY, FEMALE, MIL SERIES CONNECTOR, CRIMP, RECEPTACLE |
| AE105E11A4PA | 4 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CRIMP, RECEPTACLE |
| AE105E11A4PB | 4 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CRIMP, RECEPTACLE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| adv7152es | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ADV7152KS110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| ADV7152KS135 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| ADV7152KS170 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| ADV7152KS85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。