參數(shù)資料
型號： ADV7152
廠商： Analog Devices, Inc.
英文描述： CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器)
中文描述： 220兆赫的CMOS真彩色圖形三路10位顯存，數(shù)模轉(zhuǎn)換器（三通道，10位視頻RAM的的D / A轉(zhuǎn)換器）
文件頁數(shù)： 27/32頁
文件大小： 322K
代理商： ADV7152
ADV7152
–4–
REV. B
NOTES
1TTL input values are 0 to 3 volts, with input rise/fall times
≤ 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are
VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load
≤ 10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, I
PLL and
SYNCOUT
≤ 30 pF.
2
± 5% for all versions.
3Temperature range (T
MIN to TMAX): 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.
4Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B]; GREEN [A, B]; BLUE [A, B], Palette Selects: PS0 [A, B]; PS1 [A, B]; Pixel Controls:
SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT.
5
τ is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; τ = CLOCK = t
1 ns; 2:1 multi-
plexing,
τ = CLOCK × 2 = 2 × t
1 ns.
6These fixed values for Pipeline Delay are valid under conditions where t
10 and τ–t11 are met. If either t10 or τ–t11 are not met, the part will operate but the Pipe-
line Delay is increased by 2 clock cycles for 2:1 mode after calibration cycle is performed.
7Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the
10% and 90% points of full-scale transition. Settling time measured from the 50% point of full-scale transition to the output remaining within
±1 LSB. (Settling time
does not include clock and data feedthrough.)
8t
23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
9t
25 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging the 100 pF capacitor. This means that the time, t 25, quoted in the Timing Characteristics is the true value for the device
and as such is independent of external databus loading capacitances.
Specifications subject to change without notice.
I
SINK
+2.1V
TO
OUTPUT
PIN
I
SOURCE
100pF
Figure 1. Load Circuit for Databus Access and Relinquish Times
t
3
t
2
CLOCK
LOADOUT
(1:1 MULTIPLEXING)
LOADOUT
(2:1 MULTIPLEXING)
CLOCK
t
4
t
1
Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
PIXEL INPUT
DATA*
LOADIN
t8
t9
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
VALID
DATA
VALID
DATA
VALID
DATA
t5
t6
t7
Figure 3. LOADIN vs. Pixel Input Data
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