參數(shù)資料
型號: ADV7152
廠商: Analog Devices, Inc.
英文描述: CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器)
中文描述: 220兆赫的CMOS真彩色圖形三路10位顯存,數(shù)模轉(zhuǎn)換器(三通道,10位視頻RAM的的D / A轉(zhuǎn)換器)
文件頁數(shù): 29/32頁
文件大?。?/td> 322K
代理商: ADV7152
ADV7152
–6–
REV. B
SCKIN
END OF SCAN
LINE (N)
t13
SCKOUT
START OF SCAN
LINE (N+1)
BLANKING PERIOD
t15
t14
BLANK
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 7. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)
CLOCK
t
17
10 %
50 %
90 %
t
16
t
18
WHITE LEVEL
BLACK LEVEL
FULL SCALE
TRANSITION
ANALOG
OUTPUTS
IOR, IOR
IOG, IOG
IOB, IOB
I
PLL , SYNCOUT
NOTE:
THIS DIAGRAM IS NOT TO SCALE. FOR PURPOSES OF CLARITY, THE
ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLITUDE
W.R.T. THE CLOCK WAVEFORM.
I
PLL AND SYNCOUT ARE DIGITAL OUTPUT SIGNALS. t16 IS THE ONLY
RELEVANT OUTPUT TIMING SPECIFICATION FOR I
PLL AND SYNCOUT.
Figure 8. Analog Output Response vs. CLOCK
t20
VALID
CONTROL DATA
t21
t23
t26
t27
D0–D9
(READ MODE)
D0–D9
(WRITE MODE)
CE
R/W, C0, C1
R/W = 1
R/W = 0
t19
t22
t25
t24
Figure 9. Microprocessor Port (MPU) Interface Timing
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