參數(shù)資料
型號： ADUC7036DCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 86/132頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC7036
Rev. C | Page 57 of 132
In ADC normal power mode, the maximum ADC throughput
rate is 8 kHz. This is configured by setting the SF and AF bits in
the ADCFLT MMR to 0, with all other filtering options disabled.
As a result, 0x0000 is written to ADCFLT. Figure 24 shows a
typical 8 kHz filter response based on these settings.
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02468
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Figure 24. Typical Digital Filter Response at fADC = 8 kHz (ADCFLT = 0x0000)
A modified version of the 8 kHz filter response can be configured
by setting the running average bit (ADCFLT[14]). As a result,
an additional running-average-by-two filter is introduced on all
ADC output samples, which further reduces the ADC output
noise. In addition, by maintaining an 8 kHz ADC throughput
rate, the ADC settling time is increased by one full conversion
period. The modified frequency response for this configuration
is shown in Figure 25.
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0
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Figure 25. Typical Digital Filter Response at fADC = 8 kHz (ADCFLT = 0x4000)
At very low throughput rates, the chop enable bit in the
ADCFLT register can be enabled to minimize offset errors and,
more importantly, temperature drift in the ADC offset error.
With chop enabled, there are two primary variables (Sinc3
decimation factor and averaging factor) available to allow the
user to select an optimum filter response, but there is a trade-off
between filter bandwidth and ADC noise.
For example, with the chop enable bit (ADCFLT[15]) set to 1,
the SF value (ADCFLT[6:0]) increases to 0x1F (31 decimal) and
an AF value (ADCFLT[13:8]) of 0x16 (22 decimal) is selected,
resulting in an ADC throughput of 10 Hz. The frequency
response in this case is shown in Figure 26.
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Figure 26. Typical Digital Filter Response at fADC = 10 Hz (ADCFLT = 0x961F)
Changing SF to 0x1D and setting AF to 0x3F with the chop enable
bit still enabled configures the ADC with its minimum throughput
rate of 4 Hz in normal mode. The digital filter frequency response
with this configuration is shown in Figure 27.
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0
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Figure 27. Typical Digital Filter Response at fADC = 4 Hz (ADCFLT = 0xBF1D)
In ADC low power mode, the Σ-Δ modulator clock of the ADC
is no longer driven at 512 kHz, but is driven directly from the
on-chip, low power, 131 kHz oscillator. Subsequently, if normal
mode is used for the same ADCFLT configuration, all filter values
should be scaled by a factor of approximately 4. Therefore, it is
possible to configure the ADC for 1 Hz throughput in low power
mode. The filter frequency response for this configuration is shown
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