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參數(shù)資料
| 型號： | ADUC7036DCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC7036
Rev. C | Page 118 of 132
LIN Hardware Synchronization Control Register 0
Name: LHSCON0
Address: 0xFFFF0784
Default Value: 0x00000000
Access: Read/write
Function: This 16-bit LHS control register, in conjunction with the LHSCON1 register, is used to configure the LIN mode of operation.
Table 93. LHSCON0 MMR Bit Designations
Bit
Description
15 to 13
Reserved. These bits are reserved for future use and should be written as 0 by user software.
12
Rising edge detected interrupt disable.
Mode
Description
BSD mode
Set to 1 to disable the rising edge detected interrupt.
Cleared to 0 to enable the break rising edge detected interrupt.
LIN mode
Set to 1 to enable the rising edge detected interrupt.
Cleared to 0 to disable the break rising edge detected interrupt.
11
Break timer compare interrupt disable.
Set to 1 to disable the break timer compare interrupt.
Cleared to 0 to enable the break timer compare interrupt.
10
Break timer error interrupt disable.
Set to 1 to disable the break timer error interrupt.
Cleared to 0 to enable the break timer error interrupt.
9
LIN transceiver, standalone test mode.
Set to 1 by user code to enable the external GPIO_7 and GPIO_8 pins to drive the LIN Transceiver TxD and the LIN Transceiver
RxD, respectively, independent of the UART. The functions of GPIO_7 and GPIO_8 should first be configured by user code via
the GPIO_7 Function Select Bit 0 and GPIO_8 Function Select Bit 4 in the GP2CON register.
Cleared to 0 by user code to operate the LIN in normal mode, it is driven directly from the on-chip UART.
8
Gate UART/BSD R/W bit.
Mode
Description
UART mode
Set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the break
field and subsequent LIN sync byte are detected. This ensures that during break or sync field periods the
UART does not receive any spurious serial data that has to be flushed out of the UART before valid data
fields can be received.
Cleared to 0 by user code to enable the internal UART RxD (receive data) after the break field and
subsequent LIN sync byte have been detected so that the UART can receive the subsequent LIN data fields.
Set to 1 by user code to enable the generation of a break condition interrupt (LHSSTA[0]) on a rising edge of
the BSD bus. The break timer (LHSVAL1) starts counting on the falling edge and stops counting on the rising
edge, where an interrupt is generated, allowing user code to determine if a 0, 1, or sync pulse width has
been received. Note that the break timer generates an interrupt if the value in the LIN break timer (LHSVAL1
read value) equals the break timer compare value (LHSVAL1 write value), and if the break timer overflows.
This configuration can be used in BSD read mode to detect fault conditions on the BSD bus.
Cleared to 0 by user code to disable the generation of break condition interrupts on a rising edge of the BSD
bus. The LHS compare interrupt bit (LHSSTA[3]) is used to determine when the MCU should release the BSD
bus while transmitting data. If the break condition interrupt is still enabled, it generates an unwanted
interrupt as soon as the BSD bus is deasserted. As in BSD read mode, the break timer stops counting on a
rising edge; therefore, the break timer can also be used in this mode to allow user code to confirm the pulse
width in transmitted data bits.
7
Sync timer stop edge type bit.
Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register.
Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register.
6
Mode of operation bit.
Set to 1 by user code to select BSD mode of operation.
Cleared to 0 by user code to select LIN mode of operation.
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| ADUC7036DCPZ-RL | 功能描述:IC MCU 96K FLASH DUAL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
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