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參數(shù)資料
| 型號： | ADUC7036DCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 132/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC7036
Rev. C | Page 99 of 132
High Voltage Configuration1 Register
Name: HVCFG1
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the function of high voltage circuits on the ADuC7036. This register is not an MMR and does not
appear in the MMR memory map. It is accessed via the HVCON register interface. Data to be written to this register is loaded through
HVDAT, and data is read back from this register using HVDAT.
Table 75. HVCFG1 Bit Designations
Bit
Description
7
Voltage attenuator diagnostic enable bit.
Set to 1 to turn on a 1.29 μA current source that adds 170 mV differential voltage to the voltage channel measurement.
Cleared to 0 to disable the voltage attenuator diagnostic.
6
High voltage temperature monitor. The high voltage temperature monitor is an uncalibrated temperature monitor
located on chip, close to the high voltage circuits. This monitor is completely separate to the on-chip, precision
temperature sensor (controlled via ADC1CON[7:6]) and allows user code to monitor die temperature change close to
the hottest part of the ADuC7036 die. The monitor generates a typical output voltage of 600 mV at 25°C and has a
negative temperature coefficient of typically 2.1 mV/°C.
Set to 1 to enable the on-chip, high voltage temperature monitor. When enabled, this voltage output temperature
monitor is routed directly to the voltage channel ADC.
Cleared to 0 to disable the on-chip, high voltage temperature monitor.
5
Voltage channel short enable bit.
Set to 1 to enable an internal short (at the attenuator, before the ADC input buffers) on the voltage channel ADC and to
allow noise to be measured as a self-diagnostic test.
Cleared to 0 to disable an internal short on the voltage channel.
4
WU and STI readback enable bit.
Set to 1 to enable input capability on the external WU and STI pins. In this mode, a rising or falling edge transition on
the WU and STI pins generates a high voltage interrupt. When this bit is set, the state of the WU and STI pins can be
monitored via the HVMON register (HVMON[7] and HVMON[5]).
Cleared to 0 to disable input capability on the external WU and STI pins.
3
High voltage I/O driver enable bit.
Set to 1 to reenable high voltage I/O pins (LIN/BSD, STI, and WU) that have been disabled as a result of a short-circuit
current event (the event must last longer than 20 μs for the LIN/BSD and STI pins and longer than 400 μs for the WU
pin). This bit must also be set to 1 to reenable the WU and STI pins if they were disabled by a thermal event. It should
be noted that this bit must be set to clear any pending interrupt generated by the short-circuit event (even if the event
has passed) as well as reenabling the high voltage I/O pins.
Cleared to 0 automatically.
2
Enable/disable short-circuit protection (LIN/BSD and STI).
Set to 1 to enable passive short-circuit protection on the LIN pin. In this mode, a short-circuit event on the LIN/BSD pin
generates a high voltage interrupt, IRQ3 (if enabled in IRQEN[16]), and asserts the appropriate status bit in HVSTA but
does not disable the short-circuiting pin.
Cleared to 0 to enable active short-circuit protection on the LIN/BSD pin. In this mode, during a short-circuit event, the
LIN/BSD pin generates a high voltage interrupt (IRQ3), asserts HVSTA[16], and automatically disables the short-
circuiting pin. When disabled, the I/O pin can only be reenabled by writing to HVCFG1[3].
1
WU pin timeout (monoflop) counter enable/disable.
Set to disable the WU I/O timeout counter.
Cleared to enable a timeout counter that automatically deasserts the WU pin 1.3 sec after user code has asserted the
WU pin via HVCFG0[4].
0
WU open-circuit diagnostic enable.
Set to enable an internal WU I/O diagnostic pull-up resistor to the VDD pin, thus allowing detection of an open-circuit
condition on the WU pin.
Cleared to disable an internal WU I/O diagnostic pull-up resistor.
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