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參數(shù)資料
| 型號： | ADUC7036DCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 85/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC7036
Rev. C | Page 56 of 132
ADC COMPARATOR AND ACCUMULATOR
The incorporation of comparator logic on the I-ADC allows the
I-ADC result to generate an interrupt after a predefined number of
conversions has elapsed or a programmable threshold value has
been exceeded.
Every I-ADC result can be compared with a preset threshold
level (ADC0TH) that is set via ADCCFG[4:3]. In this case, an
MCU interrupt is generated if the absolute (sign independent)
value of the ADC result is greater than the preprogrammed
comparator threshold level. Alternatively, as an extended
function of the comparator, user code can configure a threshold
counter (ADC0THV) to monitor the number of I-ADC results
that have occurred above or below the preset threshold level. In
this case, an ADC interrupt is generated when the threshold
counter reaches a preset value that is set via ADC0TCL.
By also incorporating a 32-bit accumulator (ADC0ACC) function
that can be configured via ADCCFG[6:5], the I-ADC can add or
subtract multiple I-ADC sample results. User code can read the
accumulated value directly (ADC0ACC) without any further
software processing.
ADC SINC3 DIGITAL FILTER RESPONSE
The overall frequency response on all ADuC7036 ADCs is
dominated by the low-pass filter response of the on-chip Sinc3
digital filters. The Sinc3 filters are used to decimate the ADC
Σ-Δ modulator output data bit stream to generate a valid 16-bit
data result. The digital filter response is identical for all ADCs
and is configured via the 16-bit ADC filter register (ADCFLT).
This register determines the overall throughput rate of the ADCs.
The noise resolution of the ADCs is determined by the pro-
grammed ADC throughput rate. In the case of the current
channel ADC, the noise resolution is determined by throughput
rate and selected gain.
The overall frequency response and the ADC throughput is
dominated by the configuration of the Sinc3 filter decimation
factor (SF) bits (ADCFLT[6:0]) and the averaging factor (AF)
bits (ADCFLT[13:8]). Due to limitations on the digital filter
internal data path, there are some limitations on the allowable
combinations of SF and AF that can be used to generate a required
ADC output rate. This restriction limits the minimum ADC
update to 4 Hz in normal power mode and to 1 Hz in low power
mode. The calculation of the ADC throughput rate is detailed
in the ADCFLT bit designations table (see Table 39), and the
restrictions on allowable combinations of AF and SF values are
outlined in Table 41.
By default, setting ADCFLT = 0x0007 configures the ADCs for
a throughput of 1 kHz with all other filtering options (chop,
running average, averaging factor, and Sinc3 modify) disabled.
A typical filter response based on this default configuration is
shown in Figure 22.
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
AT
T
E
NUA
T
IO
N
(
d
B)
FREQUENCY (kHz)
07
47
4-
02
1
Figure 22. Typical Digital Filter Response at fADC = 1 kHz
(ADCFLT = 0x0007)
In addition, a Sinc3 modify bit (ADCFLT[7]) is available in the
ADCFLT register. This bit is set by user code and modifies the
standard Sinc3 frequency response to increase the filter stop-
band rejection by approximately 5 dB. This is achieved by
inserting a second notch at the location determined by
fNOTCH2 = 1.333 × fNOTCH
where fNOTCH is the location of the first notch in the response.
There is a slight increase in ADC noise if the Sinc3 modify bit is
active. Figure 23 shows the modified 1 kHz filter response when
the Sinc3 modify bit is active. The new notch is clearly visible at
1.33 kHz, as is the improvement in stop-band rejection when
compared with the standard 1 kHz response.
AT
T
E
N
UAT
IO
N
(
d
B
)
FREQUENCY (kHz)
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0.5
1.5
2.5
3.5
4.0
4.5
3.0
2.0
1.0
5.0
07
47
4-
02
2
Figure 23. Modified Sinc3 Digital Filter Response at fADC = 1 kHz
(ADCFLT = 0x0087)
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| ADUC7036DCPZ-RL | 功能描述:IC MCU 96K FLASH DUAL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
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