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參數(shù)資料
| 型號(hào)： | ADUC7036DCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 84/132頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán)，CSP |
| 包裝： | 托盤(pán) |
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ADuC7036
Rev. C | Page 55 of 132
Current Channel ADC Accumulator Register
Name: ADC0ACC
Address: 0xFFFF055C
Default Value: 0x00000000
Access: Read only
Function: This 32-bit MMR holds the current accumulator
value. The I-ADC ready bit in the ADCSTA MMR should be
used to determine when it is safe to read this MMR. The MMR
value is reset to 0 by disabling the accumulator in the ADCCFG
MMR or reconfiguring the current channel ADC.
Low Power Voltage Reference Scaling Factor Register
Name: ADCREF
Address: 0xFFFF057C
Default Value: Part specific, factory programmed
Access: Read/write. Care should be taken not to write to this
register.
Function: This MMR allows user code to correct for the initial
error of the LPM reference. Value 0x8000 corresponds to no
error when compared to the normal mode reference. The magni-
tude of the ADC result should be multiplied by the value in
ADCREF and divided by 0x8000 to compensate for the actual
value of the low power reference. If the LPM voltage reference
is 1% below 1.2 V, the value of ADCREF is approximately
0x7EB9. If the LPM voltage reference is 1% above 1.2 V, the
value of ADCREF is approximately 0x8147.
This register corrects the effective value of the LPM reference at
the temperature at which the reference is measured during the
Analog Devices, Inc., production flow, which is 25°C. There is
no change to the temperature coefficient of the LPM reference
when using the ADCREF MMR.
This register should not be used if the precision reference is
being used in low power mode (if ADCMDE[5] is set).
ADC POWER MODES OF OPERATION
The ADCs can be configured into various reduced or full
power modes of operation by changing the configuration of
ADCMDE[4:3], and the ARM7 MCU can be configured in low
power modes of operation (POWCON[5:3]). The core power
modes are independently controlled and are not related to the
ADC power modes described in the following sections.
ADC Normal Power Mode
In normal mode, the current and voltage/temperature channels
are fully enabled. The ADC modulator clock is 512 kHz and
enables the ADCs to provide regular conversion results at a rate
between 4 Hz and 8 kHz (see the ADC Filter Register section).
Both channels are under full control of the MCU and can be
reconfigured at any time. The default ADC update rate for all
channels in this mode is 1 kHz.
Note that the I-ADC and V-/T-ADC channels can be
configured to initiate periodic single conversion cycles in
normal power mode with high accuracy before returning to
ADC full power-down mode. This flexibility is facilitated by
full MCU control via the ADCMDE MMR, which ensures the
feasibility of continuous periodic monitoring of battery current,
voltage, and temperature settings while minimizing the average
dc current consumption.
In ADC normal mode, the PLL must not be powered down.
ADC Low Power Mode
In ADC low power mode, the I-ADC is enabled in a reduced
power and reduced accuracy configuration. The ADC modu-
lator clock is driven directly from the on-chip 131 kHz low
power oscillator, which allows the ADC to be configured at
update rates as low as 1 Hz (ADCFLT). The gain of the ADC
in this mode is fixed at 128.
All ADC peripheral functions (result counter, digital comparator
and accumulator) described in the ADC Normal Power Mode
section can also be enabled in low power mode.
Typically, in low power mode, only the I-ADC is configured to
run at a low update rate, continuously monitoring battery current.
The MCU is in power-down mode and wakes up when the I-ADC
interrupts the MCU. Such an interrupt occurs after the I-ADC
detects a current conversion beyond a preprogrammed threshold,
a setpoint, or a set number of conversions.
It is also possible to select either the ADC precision voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
ADC Low Power Plus Mode
In low power plus mode, the I-ADC channel is enabled in a
mode almost identical to low power mode (ADCMDE[4:3]).
However, in this mode, the I-ADC gain is fixed at 512, and the
ADC consumes an additional 200 μA (approximately) to yield
improved noise performance relative to the low power mode
setting.
All ADC peripheral functions (result counter, digital comparator,
and accumulator) described in the ADC Normal Power Mode
section can also be enabled in low power plus mode.
As in low power mode, only the I-ADC is configured to run at
a low update rate, continuously monitoring battery current. The
MCU is in power-down mode and wakes up only when the I-ADC
interrupts the MCU. This happens after the I-ADC detects a
current conversion result that exceeds a preprogrammed
threshold or a setpoint.
It is also possible to select either the ADC precision voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
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