參數(shù)資料
型號(hào)： ADUC7036DCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/132頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 96KB（48K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC7036
Rev. C | Page 111 of 132
SPI Control Register
Name: SPICON
Address: 0xFFFF0A10
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR configures the serial peripheral interface.
Table 89. SPICON MMR Bit Designations
Bit
Description
15 to 13
Reserved.
12
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, a new transfer is initiated after a stall period.
11
Loopback enable.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.
10
Slave output enable.
Set by the user to enable the slave output.
Cleared by the user to disable the slave output.
9
Slave select input enable.
Set by the user in master mode to enable the output.
Cleared by the user to disable the output.
8
SPIRX overflow overwrite enable.
Set by the user; the valid data in the SPIRX register is overwritten by the new serial byte received.
Cleared by the user; the new serial byte received is discarded.
7
SPITX underflow mode.
Set by the user to transmit the previous data.
Cleared by the user to transmit 0.
6
Transfer and interrupt mode (master mode).
Set by the user to initiate a transfer with a write to the SPITX register. An interrupt occurs when SPITX is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. An interrupt occurs when SPIRX is full.
5
LSB first transfer enable bit.
Set by the user; the LSB is transmitted first.
Cleared by the user; the MSB is transmitted first.
4
Reserved.
3
Serial clock polarity mode bit.
Set by the user; the serial clock idles high.
Cleared by the user; the serial clock idles low.
2
Serial clock phase mode bit.
Set by the user; the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user; the serial clock pulses at the end of each serial bit transfer.
1
Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
0
SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
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