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參數(shù)資料
| 型號： | ADUC7036DCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 74/132頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC7036
Rev. C | Page 46 of 132
ADC MMR INTERFACE
The ADC is controlled and configured using several MMRs that
are described in detail in the ADC Status Register section to the
All bits defined in the top eight MSBs (Bits[8:15]) of the ADCSTA
MMR are used as flags only and do not generate interrupts. All
bits defined in the lower eight LSBs (Bits[0:7]) of this MMR are
logic OR’ed to produce a single ADC interrupt to the MCU core.
In response to an ADC interrupt, user code should interrogate
the ADCSTA MMR to determine the source of the interrupt.
Each ADC interrupt source can be individually masked via the
ADCMSKI MMR described in the ADC Interrupt Mask Register
section.
All ADC result ready bits are cleared by a read of the ADC0DAT
MMR. If the current channel ADC is not enabled, all ADC result
ready bits are cleared by a read of the ADC1DAT or ADC2DAT
MMRs. To ensure that I-ADC and V-/T-ADC conversion data
are synchronous, user code should first read the ADC1DAT MMR
and then the ADC0DAT MMR. New ADC conversion results
are not written to the ADCxDAT MMRs unless the respective
ADC result ready bits are first cleared. The only exception to
this rule is the data conversion result updates when the ARM
core is powered down. In this mode, ADCxDAT registers always
contain the most recent ADC conversion result, even though
the ready bits have not been cleared.
ADC Status Register
Name: ADCSTA
Address: 0xFFFF0500
Default Value: 0x0000
Access: Read only
Function: This read only register holds general status information
related to the mode of operation or current status of the ADCs.
Table 35. ADCSTA MMR Bit Designations
Bit
Description
15
ADC calibration status.
Set automatically in hardware to indicate that an ADC calibration cycle has been completed.
Cleared after ADCMDE is written to.
14
ADC temperature conversion error.
Set automatically in hardware to indicate that a temperature conversion overrange or underrange has occurred. The conversion
result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.
13
ADC voltage conversion error.
Set automatically in hardware to indicate that a voltage conversion overrange or underrange has occurred. The conversion result is
clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
12
ADC current conversion error.
Set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. The conversion result is
clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.
11 to 5
Not used. These bits are reserved for future functionality and should not be monitored by user code.
4
Current channel ADC comparator threshold. Valid only if the current channel ADC comparator is enabled via the ADCCFG MMR.
Set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR. However, if the
ADC threshold counter is used (ADC0TCL), this bit is set only when the specified number of I-ADC conversions equals the value in
the ADC0THV MMR.
Cleared automatically by hardware when reconfiguring the ADC or if the comparator is disabled.
3
Current channel ADC overrange bit.
Set by hardware if the overrange detect function is enabled via the ADCCFG MMR and the I-ADC input is grossly (>30%
approximate) over range. This bit is updated every 125 μs.
Cleared by software only when ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR.
2
Temperature conversion result ready bit.
Set by hardware, if the temperature channel ADC is enabled, as soon as a valid temperature conversion result is written in the
temperature data register (ADC2DAT MMR). It is also set at the end of a calibration.
Cleared by reading either ADC2DAT or ADC0DAT.
1
Voltage conversion result ready bit.
Set by hardware, if the voltage channel ADC is enabled, as soon as a valid voltage conversion result is written in the voltage data
register (ADC1DAT MMR). It is also set at the end of a calibration.
Cleared by reading either ADC1DAT or ADC0DAT.
0
Current conversion result ready bit.
Set by hardware, if the current channel ADC is enabled, as soon as a valid current conversion result is written in the current data
register (ADC0DAT MMR). It is also set at the end of a calibration.
Cleared by reading ADC0DAT.
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