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參數(shù)資料
| 型號(hào)： | ADUC7036DCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 83/132頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC7036
Rev. C | Page 54 of 132
Voltage Channel ADC Gain Calibration Register
Name: ADC1GN
Address: 0xFFFF0540
Default Value: Part specific, factory programmed
Access: Read/write
Function: This gain MMR holds a 16-bit gain calibration
coefficient for scaling a voltage channel conversion result. The
register is configured at power-on with a factory default value.
However, this register is automatically overwritten if a gain
calibration of the voltage channel is initiated by the user via bits
in the ADCMDE MMR. User code can write to this calibration
register only if the ADC is in idle mode. An ADC must be
enabled and in idle mode before being written to any offset or
gain register. The ADC must be in idle mode for at least 23 μs.
Temperature Channel ADC Gain Calibration Register
Name: ADC2GN
Address: 0xFFFF0544
Default Value: Part specific, factory programmed
Access: Read/write
Function: This gain MMR holds a 16-bit gain calibration
coefficient for scaling a temperature channel conversion result.
The register is configured at power-on with a factory default
value. However, this register is automatically overwritten if a
gain calibration of the temperature channel is initiated by the
user via bits in the ADCMDE MMR. User code can write to this
calibration register only if the ADC is in idle mode. An ADC
must be enabled and in idle mode before being written to any
offset or gain register. The ADC must be in idle mode for at
least 23 μs.
Current Channel ADC Result Counter Limit Register
Name: ADC0RCL
Address: 0xFFFF0548
Default Value: 0x0001
Access: Read/write
Function: This 16-bit MMR sets the number of conversions
that are required before an ADC interrupt is generated. By
default, this register is set to 0x0001. The ADC counter function
must be enabled via the ADC result counter enable bit in the
ADCCFG MMR.
Current Channel ADC Result Count Register
Name: ADC0RCV
Address: 0xFFFF054C
Default Value: 0x0000
Access: Read only
Function: This 16-bit, read only MMR holds the current number
of I-ADC conversion results. It is used in conjunction with
ADC0RCL to mask I-ADC interrupts, generating a lower interrupt
rate. When ADC0RCV = ADC0RCL, the value in ADC0RCV
resets to 0 and recommences counting. It can also be used in
conjunction with the accumulator (ADC0ACC) to allow an
average current calculation to be undertaken. The result counter is
enabled via ADCCFG[0]. This MMR is also reset to 0 when the
I-ADC is reconfigured, that is, when the ADC0CON or ADCMDE
is written.
Current Channel ADC Threshold Register
Name: ADC0TH
Address: 0xFFFF0550
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR sets the threshold against which the
absolute value of the I-ADC conversion result is compared. In
unipolar mode, ADC0TH[15:0] are compared, and in twos
complement mode, ADC0TH[14:0] are compared.
Current Channel ADC Threshold Count Limit Register
Name: ADC0TCL
Address: 0xFFFF0554
Default Value: 0x01
Access: Read/write
Function: This 8-bit MMR determines how many cumulative
(that is, values that are below the threshold decrement or that
reset the count to 0) I-ADC conversion result readings above
ADC0TH must occur before the I-ADC comparator threshold
bit is set in the ADCSTA MMR, generating an ADC interrupt.
The I-ADC comparator threshold bit is asserted as soon as
ADC0THV = ADC0TCL.
Current Channel ADC Threshold Count Register
Name: ADC0THV
Address: 0xFFFF0558
Default Value: 0x00
Access: Read only
Function: This 8-bit MMR is incremented every time the
absolute value of an I-ADC conversion result is |I| ≥ ADC0TH.
This register is decremented or reset to 0 every time the
absolute value of an I-ADC conversion result is |I| < ADC0TH.
The configuration of this function is enabled via the current
channel ADC comparator bits in the ADCCFG MMR.
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