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| 型號(hào)： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 82/128頁(yè) |
| 文件大小： | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 57 of 128
ADC Configuration Register :
Name :
ADCCFG
Address :
0xFFFF051C
Default Value :
0x00
Access :
Read/Write
Function :
The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs.
Table 30: ADCCFG MMR Bit Designations
Bit
Description
7
Analog Ground Switch Enable
This bit is set to ‘1’ by user software to connect the external ‘GND_SW’ pin (pin#15) to an internal analog ground reference
point. This bit can be used to connect and disconnect external circuits and components to ground under program
control and thereby minimize dc current consumption when the external circuit or component is not being used.
This bit is used in conjunction with ADCMDE[6] to select a 20K
resistor to ground.
6, 5
Current Channel (32-bit) Accumulator Enable
0, 0
Accumulator Disabled and reset to 0
0, 1
Accumulator Active
Positive current values are added to accumulator total, accumulator can overflow if allowed run for > 65535
conversions
Negative current values are subtracted from accumulator total, accumulator is clamped to a
minimum value of 0
1, 0
Accumulator Active
Positive current values are added to accumulator total, accumulator can overflow if allowed run for > 65535
conversions
The absolute values of Negative current are subtracted from accumulator total, accumulator in this mode will
continue to accumulate negatively, below 0
1, 1
Accumulator and Accumulator Comparator Enabled
This mode is the same as Mode |1,0|, but with the Accumulator Comparator enabled.
4, 3
Current Channel ADC Comparator Enable
0, 0
Comparator Disabled
0, 1
Comparator Active, Interrupt asserted if absolute value of I-ADC conversion result |I| >= ADC0TH
1, 0
Comparator-Count Mode Active, Interrupt asserted if absolute value of an I-ADC conversion result |I| >=
ADC0TH for #ADC0TCL conversions. A conversion value |I| < ADC0TH will reset the threshold counter value
(ADC0THV) to 0
1, 1
Comparator-Count Mode Active, Interrupt asserted if absolute value of an I-ADC conversion result |I| >=
ADC0TH for #ADC0TCL conversions. A conversion value |I| < ADC0TH will decrement the threshold counter
value (ADC0THV) towards 0.
2
Current Channel ADC OverRange Enable
Set by user to enable a ‘coarse’ comparator on the Current Channel ADC. If the current reading is grossly (>30% approx.)
over-ranged for the active gain setting, then the over range bit in the ADCSTA MMR is set. The current must be outside
this range for greater than 125usecs for the flag to be set.
This feature should not be used in ADC Low Power Mode
1
ADC FIFO Enable
This bit is set to 1 by user code to enable ADC FIFO on Current and Voltage ADC Channels. The FIFO function allows up to
32 current and voltage ADC results to be stored in an on-chip FIFO. The current status of the FIFO is reflected by 3 bits in
the ADCSTA register.
If more than 32 results are stored in the FIFO, the contents of the FIFO may be corrupted.
0
Current Channel ADC, Result Counter Enable
Set by user to enable the result count mode. In this mode an I-ADC interrupt will only be generated when
ADC0RCV=ADC0RCL. This allows the I-ADC to continuously monitor current but only interrupt the MCU core after a
defined number of conversions. It should be noted that unless the ADC FIFO is enabled (ADCCNG[1]=1), only the last
conversion value will be available (intermediate I-ADC conversion results are not stored) when the ADC counter interrupt
occurs. The Voltage and Temperature ADCs will also continue to convert if enabled but again only the last conversion
result will be available (intermediate V/T-ADC conversion results are not stored) when the ADC counter interrupt occurs
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