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參數(shù)資料
| 型號： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 102/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 75 of 128
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 15 interrupt sources on the ADuC7032 which are
controlled by the Interrupt Controller. Most interrupts are
generated from the on-chip peripherals such as the ADC,
UART, etc.. The ARM7TDMI CPU core will only recognize
interrupts as one of two types, a normal interrupt request IRQ
and a fast interrupt request FIQ. All the interrupts can be
masked separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, four
dedicated to IRQ, four dedicated to FIQ. An additional MMR is
used to select the programmed interrupt source. The bits in
each IRQ and FIQ registers represent the same interrupt source
as described in Table 41.
IRQSTA/FIQSTA should be saved immediately upon entering
the ISR ( Interrupt Service Routine ) to ensure that all valid
interrupt sources are serviced.
The interrupt generation route through the ARM7TDMI core
is shown in Figure 29.
Consider the example of Timer0 which is configured to
generate a timeout every 1ms.
After the first 1ms timeout, FIQSIG/IRQSIG[2] will be set and
will only be cleared by writing to T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN, then
FIQSTA/IRQSTA[2] will not be set and an interrupt will not
occur.
If Timer0 is enabled in either IRQEN or FIQEN, then either
FIQSTA/IRQSTA[2] will be set and either an FIQ or an IRQ
interrupt will occur.
Please note that the IRQ and FIQ interrupt bit definitions in the
CPSR only control interrupt recognition by the ARM Core, not
by the peripherals.
For example, if Timer2 is confirgured to generate an IRQ via
IRQEN, the IRQ interrupt bit is set ( Disabled ) in the CPSR
and the ADuC7032 is powered down. When an interrupt
occurs, the peripherals will be woken, but the ARM core will
remain powered down. This is equivalent to POWCON = 0x71.
The ARM Core can only be powered up by a reset event if this
occurs.
Table 41 : IRQ/FIQ MMRs bit description
Bit
Description
For more information please refer to:
0
All interrupts OR’ed
1
SWI:
not used in IRQEN/CLR and FIQEN/CLR
2
Timer 0
Timer0 – Life-Time timer Page 78
3
Timer 1
Timer1
Page 79
4
Timer 2 - Wake Up timer
Timer2 - Wake-Up Timer Page 82
5
Timer 3 - Watchdog Timer
Timer3 - Watchdog Timer Page 83
6
Reserved and should be written as zero
7
LIN Hardware
LIN (Local Interconnect Network ) INTERFACE Page 115
8
Flash/EE Interrupt
Flash/EE memory Control Interface Page 31
9
PLL Lock
ADuC7032 System Clocks Page 68
10
ADC
16-Bit Σ Analog to Digital Converters Page 44
11
UART
UART SERIAL INTERFACE Page 105
12
SPI
SERIAL PERIPHERAL INTERFACE Page 112
13
XIRQ0
( GPIO IRQ 0 )
General Purpose I/O Page 84
14
XIRQ1
( GPIO IRQ 1 )
General Purpose I/O Page 84
15
Reserved and should be written as zero
16
IRQ3 High Voltage IRQ
High Voltage Interrupt
17
XIRQ4
( GPIO IRQ 4 )
General Purpose I/O Page 84
18
XIRQ5
( GPIO IRQ 5 )
General Purpose I/O Page 84
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