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參數(shù)資料
| 型號： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 80/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 55 of 128
ADC Filter Register :
Name :
ADCFLT
Address :
0xFFFF0518
Default Value :
0x0007
Access :
Read/Write
Function :
The ADC Filter MMR is an 16-bit register that controls the speed and resolution of the on-chip ADCs.
Note:
If ADCFLT is modified, the Current, Voltage and Temperature ADCs are reset. An additional time of 60us per
enabled ADC is required before the first ADC result is available.
Table 27 : ADCFLT MMR Bit Designations
Bit
Description
15
Chop enable
Set by user to enable system chopping of all active ADCs. When this bit is set the ADC will have very low offset errors and
drift but the ADC output rate will be reduced by a factor of 3 if AF=0 (see Sinc3 Decimation Factor bits below). If AF
≠ 0,
then ADC output update rate will be the same with chop on or off. When chop is enabled, the settling time is 2 output
periods.
Note: Should only be used with SF > 1
14
Running Average
Set by user to enable a running average by 2 function reducing ADC noise. This function is automatically enabled when
chopping is active. It is an optional feature when chopping is inactive and if enabled (when chopping is inactive) does
not reduce ADC output rate but will increase the settling time by 1 conversion period.
Cleared by user to disable the running average function.
13 - 8
Averaging Factor ( AF )
The value written to these bits is use to implement a programmable 1st order Sinc post filter. The averaging factor can
further reduce ADC noise at the expense of output rate as described in Sinc Decimation Factor bits below.
7
Sinc3 Modify
Set by user to modify the standard Sinc3 frequency response to increase the filter stopband rejection by 5dBs approx.
This is achieved by inserting a second notch (NOTCH2) at FNOTCH2 = 1.333 * FNOTCH where FNOTCH is the location of the 1st
notch in the response.
6 – 0
Sinc3 Decimation Factor (SF)
The value (SF) written in these bits controls the over sampling (decimation factor) of the Sinc3 filter. The output rate from
the Sinc3 filter is given by
FADC = ( 512,000 / ( [SF+1] X 64 )) Hz when the CHOP bit (bit#15 above) = 0 and AF=0 (note AF = Averaging Factor)
Note : this is valid for all SF values <= 125
For SF= 126, FADC is forced to 60Hz
For SF= 127, FADC is forced to 50Hz
For information on calculating the FADC for SF ( other than 126 and 127 ) and AF values please refer to
Table 28.
Note:
- Due to limitations on the digital filter internal data-path, there are some limitations on the combinations of SF(Sinc3
Decimation Factor) and AF(Averaging Factor) that can be used to generate a required ADC output rate. This
restriction limits the minimum ADC update in Normal Power Mode to 4Hz or 1Hz in Low Power Mode. If all three ADCs
are enabled, then the minimum value of SF written by user code must be 1
- In low power mode and low power-plus mode, the ADC is driven directly by the low power oscillator (131KHz) and
not 512KHz. All FADC calculations should be divided by 4 (approx).
- For optimal ADC performance, SF should be increased before AF is used.
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