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| 型號(hào)： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 59/128頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 36 of 128
In Summary, there are three levels of protection:
- Temporary Protection can be set and removed by writing
directly into FEExHID MMR. This register is volatile and
therefore
protection will only be in place while the part
remains powered on. This protection is not reloaded after
a power cycle.
- Keyed Permanent Protection can be set via FEExPRO
which is used to lock the protection configuration. The
software key used at the start of the required FEExPRO
write sequence is saved once and MUST subsequently be
used for any subsequent access of the FEExHID or
FEExPRO MMRs. A mass erase will set the key back to
0xFFFF but will also erase the entire user code space.
- Permanent Protection can be set via FEExPRO, similarily
to Keyed Permanent Protection, the only difference been
that the software key used is 0xDEADDEAD. Once the
FEExPRO write sequence is saved, only a mass erase will
set the key back to 0xFFFFFFFF. This will also erase the
entire user code space.
Sequence to write the key and set permanent protection:
1.
Write in FEExPRO corresponding to the pages to be
protected.
2.
Write the new (user defined) 32 bit key in FEExADR [ Bits
31-16 ] and FEExDAT [ Bits 15-0 ].
3.
Write 1,0 in FEExMOD[6:5] and set FEExMOD[3].
4.
Run the write key command 0x0C in FEExCON.
To remove or modify the protection the same sequence can be
used with a modified value of FEExPRO.
The sequence above is illustrated in the following example, this
protects writing pages 4 and 5of the FLASH:
FEExPRO =0xFFFFFFFB;
//Protect pages 4 and 5
FEExADR =0x66BB;
//32 bit key value [Bits 31-16]
FEExDAT =0xAA55;
//32 bit key value [Bits 15-0]
FEExMOD = 0x0048
// Lock Security Sequence
FEExCON = 0x0C;
// Write key command
while (FEExSTA & 0x04){}
//Wait for command to finish
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as:
1. Initial page erase sequence.
2. Read/verify sequence a single Flash/EE.
3. Byte program sequence memory.
4. Second read/verify sequence endurance cycle.
In reliability qualification, every half word (16-bit wide)
location of the three pages(top, middle and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the parts’ Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 . the results allow
the specification of a minimum endurance figure over supply,
temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Also note that retention
lifetime, based on an activation energy of 0.6 eV, derates with TJ
as shown in Figure 12.
150
300
450
600
30
40
55
70
85
100
125
135
150
RE
T
E
NT
IO
N
(
Y
ea
rs
)
0
04
95
5-
08
5
JUNCTION TEMPERATURE (°C)
Figure 12. Flash/EE Memory Data Retention
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