參數(shù)資料
型號(hào): ADSP-TS202S
廠商: Analog Devices, Inc.
英文描述: TigerSHARC Embedded Processor
中文描述: TigerSHARC系列嵌入式處理器
文件頁數(shù): 8/40頁
文件大?。?/td> 615K
代理商: ADSP-TS202S
Rev. PrB
|
Page 8 of 40
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December 2003
ADSP-TS202S
Preliminary Technical Data
LINK PORTS (LVDS)
The DSP’s four full-duplex link ports each provide additional
four-bit receive and four-bit transmit I/O capability, using Low-
Voltage, Differential-Signal (LVDS) technology. With the abil-
ity to operate at a double data rate—latching data on both the
rising and falling edges of the clock—running at 500 MHz, each
link port can support up to 500M bytes per second per direc-
tion, for a combined maximum throughput of 4G bytes per
second.
The link ports provide an optional communications channel
that is useful in multiprocessor systems for implementing point-
to-point interprocessor communications. Applications can also
use the link ports for booting.
Each link port has its own triple-buffered quad-word input and
double-buffered quad-word output registers. The DSP’s core
can write directly to a link port’s transmit register and read from
a receive register, or the DMA controller can perform DMA
transfers through eight (four transmit and four receive) dedi-
cated link port DMA channels.
Each link port direction has three signals that control its opera-
tion. For the transmitter, LxCLKOUT is the output transmit
clock, LxACKI is the handshake input to control the data flow,
and the LxBCMPO output indicates that the block transfer is
complete. For the receiver, LxCLKIN is the input receive clock,
LxACKO is the handshake output to control the data flow, and
Figure 4. ADSP-TS202S Shared Memory Multiprocessing System
CLKS/REFS
ADDR31–0
DATA63–0
BR1
BR7–2,0
ADDR31–0
DATA63–0
BR0
BR7–1
BMS
CPA
CONTROL
ADSP-TS202S #0
CONTROL
ADSP-TS202S #1
ADSP-TS202S #7
ADSP-TS202S #6
ADSP-TS202S #5
ADSP-TS202S #4
ADSP-TS202S #3
ADSP-TS202S #2
RESET
RST_IN
CLKS/REFS
RST_OUT
ID2–0
SCLK_V
REF
V
REF
SCLKRAT2–0
SCLK
000
CLOCK
REFERENCE
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
CS
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
WE
ADDR
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
RD
MS1–0
ACK
ID2–0
RST_IN
001
HBG
MSH
HBR
BOFF
BRST
WRH/L
C
A
D
C
A
D
SDRAM
MEMORY
(OPTIONAL)
MSSD3–0
IORD
IOWR
IOEN
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
DMAR3–0
DPA
LINK
DEVICES
(4 MAX)
(OPTIONAL)
LxCLKINP/N
LxACKO
LxBCMPI
LxDATI3–0P/N
LxBCMPO
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
TMR0E
BM
CONTROLIMP1–0
DS2–0
LINK
IRQ3–0
FLAG3–0
LINK
BUSLOCK
CLOCK
JTAG
POR_IN
REFERENCE
LINK
DEVICES
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