參數(shù)資料
型號： ADSP-TS202S
廠商： Analog Devices, Inc.
英文描述： TigerSHARC Embedded Processor
中文描述： TigerSHARC系列嵌入式處理器
文件頁數(shù)： 12/40頁
文件大?。?/td> 615K
代理商： ADSP-TS202S
Rev. PrB
|
Page 12 of 40
|
December 2003
ADSP-TS202S
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS202S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. Use the
AC specification for asynchronous signals when the system
design requires predictable, cycle-by-cycle behavior for these
signals.
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these
pins to get to their internal pullup or pulldown state. Some pins
have an internal pullup or pulldown resistor (±30% tolerance)
that maintains a known value during transitions between differ-
ent drivers.
Table 3. Pin Definitions—Clocks and Reset
Signal
SCLKRAT2–0
Type
I (pd)
Term
au
Description
Core Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is user-program-
mable using the SCLKRATx pins to the values shown in
Table 4
. These pins must have
a constant value while the DSP is powered. The core clock rate (CCLK) is the instruction
cycle rate.
System Clock Input. The DSP’s system input clock for cluster bus.The core clock rate
is user-programmable using the SCLKRATx pins.
For more information, see Clock
Domains on page 9.
Reset. Sets the DSP to a known state and causes program to be in idle state. RST_IN
must be asserted a specified time according to the type of reset operation. For details,
see
Reset and Booting on page 9
,
Table 17 on page 23
, and
Figure 10 on page 24
.
Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN.
Power On Reset for internal DRAM. Connect to RST_OUT.
SCLK
I
1
au
RST_IN
I/A
au
RST_OUT
POR_IN
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
O
I/A
au
au
1
For more information on SCLK and SCLK_V
REF
on revision 0.x silicon, see the
EE-179: ADSP-TS20x TigerSHARC System Design Guidelines
on the Analog Devices website
www.analog.com
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