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| 型號： | ADSP-TS202S |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | TigerSHARC Embedded Processor |
| 中文描述： | TigerSHARC系列嵌入式處理器 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 615K |
| 代理商： | ADSP-TS202S |
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ADSP-TS202S
Preliminary Technical Data
Rev. PrB
|
Page 23 of 40
|
December 2003
TIMING SPECIFICATIONS
With the exception of DMAR3–0, IRQ3–0, TMR0E, and
FLAG3–0 (input only) pins, all AC timing for the ADSP-TS202S
processor is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSP-
TS202S processor has few calculated (formula-based) values.
For information on AC timing, see
General AC Timing on
page 23
. For information on Link port transfer timing, see
Link
Port Low-Voltage, Differential-Signal (LVDS) Electrical Char-
acteristics and Timing on page 27
.
General AC Timing
Timing is measured on signals when they cross the 1.25 V level
as described in
Figure 11 on page 26
. All delays (in nanosec-
onds) are measured between the point that the first signal
reaches 1.25 V and the point that the second signal reaches
1.25 V.
The general AC timing data appears in
Table 18
and
Table 22
.
The AC asynchronous timing data for the IRQ3–0, DMAR3–0,
FLAG3–0, and TMR0E pins appears in
Table 17
.
Table 17. AC Asynchronous Signal Specifications (all values in this table are in nanoseconds)
Name
IRQ3–0
1
DMAR3–0
1
FLAG3–0
2
TMR0E
3
Description
Interrupt Request
DMA Request
FLAG3–0 Input
Timer 0 Expired
Pulsewidth Low (min)
2×t
SCLK
ns
2×t
SCLK
ns
2×t
SCLK
ns
4×t
SCLK
ns
Pulsewidth High (min)
2×t
SCLK
ns
2×t
SCLK
ns
2×t
SCLK
ns
–
1
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.
2
For output specifications on FLAG3–0 pins, see
Table 22
.
3
This pin is a strap option. During reset, an internal resistor pulls the pin low.
Table 18. Reference Clocks
Signal
Type
Description
Speed
Grade
(MHz)
Clock
Cycle
Min (ns)
Clock
Cycle
Max (ns)
Clock
High
Min (ns)
Clock
Low
Min (ns)
Input
Jitter
Tolerance
(ps)
–
100
CCLK
1
SCLK
2,3,4
–
I
Core Clock
System Clock
500
All
2.0
Greater of 8
or CCLK×4
Greater of 30
or CCLK×4
12.5
50
–
–
{40% to 60%
Duty Cycle}
TCK
I
Test Clock (JTAG)
All
–
12
12
–
1
CCLK is the internal DSP clock or instruction cycle time. The period of this clock is equal to the System Clock (SCLK) period divided by the System Clock Ratio (SCLKRAT2–0).
For information on available internal DSP clock rates, see the
Ordering Guide on page 40
.
2
Actual input jitter should be combined with ac specifications for accurate timing analysis.
3
For more information, see
Table 3 on page 12
.
4
For more information, see Clock Domains on page 9.
Table 19. Power-Up Reset Timing
Parameter
Timing Requirements
t
VDD_DRAM1
t
VDD_DRAM_RAMP
Min
Max
Units
V
DD_DRAM
Stable After V
DD
, V
DD_A
, V
DD_IO
Stable
V
DD_DRAM
Supply Rise Time
0
ms
ms
0.2
1
Applies only when the internal DRAM regulator is disabled (ENEDREG=0)
Figure 8. Power-Up Timing
V
DD
V
DD_A
V
DD_IO
V
DD_DRAM
t
VDD_DRAM_RAMP
t
VDD_DRAM
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| ADSP-TS202SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-TS203SABP-050 | 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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