參數(shù)資料
型號： ADSP-TS202S
廠商： Analog Devices, Inc.
英文描述： TigerSHARC Embedded Processor
中文描述： TigerSHARC系列嵌入式處理器
文件頁數(shù)： 16/40頁
文件大?。?/td> 615K
代理商： ADSP-TS202S
Rev. PrB
|
Page 16 of 40
|
December 2003
ADSP-TS202S
Preliminary Technical Data
SDA10
O/T
(pu_0)
I/O/T
(pu_m/
pd_m)
nc
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation
while the DSP executes non-SDRAM transactions.
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend
modes. A slave DSP in a multiprocessor system does not have the pullup or pulldown.
A master DSP (or ID=0 in a single processor system) has a pullup before granting the
bus to the host, except when the SDRAM is put in self refresh mode. In self refresh
mode, the master has a pulldown before granting the bus to the host.
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to
execute according to SDRAM specification.
SDCKE
nc
SDWE
I/O/T
(pu_0)
nc
Table 9. Pin Definitions—JTAG Port
Signal
EMU
Type
O/OD
Term
nc
1
Description
Emulation. Connected to the DSP’s JTAG emulator target board connector only.
TCK
TDI
I
I
(pu_ad)
O/T
epd or epu
1
nc
1
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
Test Data Input (JTAG). A serial data input of the scan path.
TDO
nc
1
Test Data Output (JTAG). A serial data output of the scan path.
TMS
I
(pu_ad)
I/A
(pu_ad)
nc
1
Test Mode Select (JTAG). Used to control the test state machine.
TRST
au
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low
after power up for proper device operation. For more information, see
Reset and
Booting on page 9
.
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
1
See the reference
on page 11
to the JTAG emulation technical reference EE-68.
Table 8. Pin Definitions—External Port SDRAM Controller (Continued)
Signal
Type
Term
Description
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
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