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參數(shù)資料
| 型號： | ADSP-TS202S |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | TigerSHARC Embedded Processor |
| 中文描述： | TigerSHARC系列嵌入式處理器 |
| 文件頁數(shù)： | 3/40頁 |
| 文件大?。?/td> | 615K |
| 代理商： | ADSP-TS202S |
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ADSP-TS202S
Preliminary Technical Data
Rev. PrB
|
Page 3 of 40
|
December 2003
GENERAL DESCRIPTION
The ADSP-TS202S TigerSHARC processor is an ultra-high per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting 32- and 40-bit floating-point and support-
ing 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new
standard of performance for digital signal processors. The
TigerSHARC static superscalar architecture lets the DSP exe-
cute up to four instructions each cycle, performing twenty-four
16-bit fixed-point operations or six floating-point operations.
Four independent 128-bit wide internal data buses, each con-
necting to the six 2M bit memory banks, enable quad-word
data, instruction, and I/O accesses and provide 28G bytes per
second of internal memory bandwidth. Operating at 500 MHz,
the ADSP-TS202S processor’s core has a 2.0 ns instruction cycle
time. Using its Single-Instruction, Multiple-Data (SIMD) fea-
tures, the ADSP-TS202S processor can perform four billion 40-
bit MACs or one billion 80-bit MACs per second.
Table 1
shows
the DSP’s performance benchmarks.
The ADSP-TS202S processor is code-compatible with the other
TigerSHARC processors.
The Functional Block Diagram
on page 1
shows the ADSP-
TS202S processor’s architectural blocks. These blocks include:
Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and associated
Data Alignment Buffers (DABs)
Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing and a status register
A program sequencer with Instruction Alignment Buffer
(IAB) and Branch Target Buffer (BTB)
An interrupt controller that supports hardware and soft-
ware interrupts, supports level- or edge-triggers, and
supports prioritized, nested interrupts
Four 128-bit internal data buses, each connecting to the six
2M bit memory banks
On-chip DRAM (12M bit)
An external port that provides the interface to host proces-
sors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAM
A 14 channel DMA controller
Four full-duplex LVDS link ports
Two 64-bit interval timers and timer expired pin
A 1149.1 IEEE compliant JTAG test access port for on-chip
emulation
Figure 2 on page 3
shows a typical single-processor system with
external SRAM and SDRAM.
Figure 4 on page 8
shows a typical
multiprocessor system.
The TigerSHARC DSP uses a Static Superscalar
*
architecture.
This architecture is superscalar in that the ADSP-TS202S pro-
cessor’s core can execute simultaneously from one to four 32-bit
instructions encoded in a Very Large Instruction Word (VLIW)
instruction line using the DSP’s dual compute blocks. Because
Table 1. General Purpose Algorithm Benchmarks
at 500 MHz
Benchmark
Speed
Clock
Cycles
32-bit Algorithm, one billion MACs/s peak performance
1K Point Complex FFT
1
(Radix2)
64K Point Complex FFT
1
(Radix2)
FIR Filter (per real tap)
[8 × 8][8 × 8] Matrix Multiply (Complex,
Floating-point)
16-bit Algorithm, four billion MACs/s peak performance
256 Point Complex FFT
1
(Radix 2)
I/O DMA Transfer Rate
External port
Link ports (each)
1
Cache preloaded
18.8 μs
2.8 ms
1 ns
2.8 μs
9419
1397544
0.5
1399
1.9 μs
928
1G bytes/s
1G bytes/s
n/a
n/a
Figure 2. ADSP-TS202S Single-Processor System With External SDRAM
*
Static Superscalar is a trademark of Analog Devices, Inc.
BOFF
CONTROLIMP1–0
TMR0E
DS2–0
DMAR3–0
HBG
HBR
DMA DEVICE
(OPTIONAL)
DATA
MSH
FLAG3–0
ID2–0
MSSD3–0
IOEN
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
IORD
IOWR
IRQ3–0
SCLK
SCLKRAT2–0
SCLK_V
REF
V
REF
BM
BUSLOCK
JTAG
SDRAM
MEMORY
(OPTIONAL)
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
POR_IN
ADSP-TS202S
RST_IN
BMS
CLOCK
LINK
DEVICES
(4 MAX)
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
CS
ADDR
(MEMORY
OE
WE
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
MS1–0
BR7–0
CPA
DPA
DATA63–0
DATA
ADDR
CS
ACK
ADDR31–0
D
C
A
BRST
REFERENCE
RD
WRH/WRL
LxCLKINP/N
LxACKO
LxBCMPI
LxDATI3–0P/N
LxBCMPO
RST_OUT
REFERENCE
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參數(shù)描述 |
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| ADSP-TS202SABP-050 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 500MHz 500MIPS 576-Pin TEBGA 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 500MHZ 500MIPS 576PIN TEBGA - Trays |
| ADSP-TS202SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS202SABP-X | 制造商:Analog Devices 功能描述: |
| ADSP-TS202SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-TS203SABP-050 | 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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