參數(shù)資料
型號(hào)： ADSP-TS202S
廠商： Analog Devices, Inc.
英文描述： TigerSHARC Embedded Processor
中文描述： TigerSHARC系列嵌入式處理器
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 615K
代理商： ADSP-TS202S
ADSP-TS202S
Preliminary Technical Data
Rev. PrB
|
Page 17 of 40
|
December 2003
Table 10. Pin Definitions—Flags, Interrupts, and Timer
Signal
FLAG3–0
Type
I/O/A
(pu)
Term
nc
Description
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin
can be configured individually for input or for output. FLAG3–0 are inputs after power-up
and reset.
Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0 pins
can be independently set for edge-triggered or level-sensitive operation. After reset, these
pins are disabled unless the IRQ3–0 strap option and interrupt vectors are initialized for
booting.
Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.
For more information, see
Table 15 on page 19
.
IRQ3–0
I/A
(pu)
nc
TMR0E
O
au
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
Table 11. Pin Definitions—Link Ports
Signal
LxDATO3–0P
LxDATO3–0N
LxCLKOUTP
LxCLKOUTN
LxACKI
Type
O
O
O
O
I (pd)
Term
nc
nc
nc
nc
nc
Description
Link Ports 3–0 Data 3–0 Transmit LVDS P
Link Ports 3–0 Data 3–0 Transmit LVDS N
Link Ports 3–0 Transmit Clock LVDS P
Link Ports 3–0 Transmit Clock LVDS N
Link Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission
Link Ports 3–0 Block Completion. When the transmission is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed. At reset, the
L1BCMPO, L2BCMPO, and L3BCMPO pins are strap pins. For more information, see
Table 15 on page 19
.
Link Ports 3–0 Data 3–0 Receive LVDS P
Link Ports 3–0 Data 3–0 Receive LVDS N
Link Ports 3–0 Receive Clock LVDS P
Link Ports 3–0 Receive Clock LVDS N
Link Ports 3–0 Transmit Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
Link Ports 3–0 Block Completion. When the reception is executed using DMA, this
signal indicates to the transmitter that the receive block is completed.
LxBCMPO
O
nc
1
LxDATI3–0P
LxDATI3–0N
LxCLKINP
LxCLKINN
LxACKO
I
I
I/A
I/A
O
V
DD_IO
V
DD_IO
V
DD_IO
V
SS
nc
LxBCMPI
I
V
SS
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
1
The L1BCMPO and L2BCMPO pins have different termination requirements on revision 0.x silicon, see the
EE-179: ADSP-TS20xS TigerSHARC System Design Guidelines
on the Analog Devices website (
).
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