參數(shù)資料
型號(hào): ADSP-TS202S
廠商: Analog Devices, Inc.
英文描述: TigerSHARC Embedded Processor
中文描述: TigerSHARC系列嵌入式處理器
文件頁(yè)數(shù): 25/40頁(yè)
文件大?。?/td> 615K
代理商: ADSP-TS202S
ADSP-TS202S
Preliminary Technical Data
Rev. PrB
|
Page 25 of 40
|
December 2003
Table 22. AC Signal Specifications
(all values in this table are in nanoseconds)
Name
Description
I
(
I
(
O
(
O
(
O
(
1
O
(
1
R
ADDR31–0
DATA63–0
MSH
MSSD3–0
MS1–0
RD
WRL
WRH
ACK
External Address Bus
External Data Bus
Memory Select HOST Line
Memory Select SDRAM Lines
Memory Select for Static Blocks
Memory Read
Write Low Word
Write High Word
Acknowledge for Data Hi to Low
Acknowledge for Data Low to High
SDRAM Clock Enable
Row Address Select
Column Address Select
SDRAM Write Enable
Low Word SDRAM Data Mask
High Word SDRAM Data Mask
SDRAM ADDR10
Host Bus Request
Host Bus Grant
Back Off Request
Bus Lock
Burst pin
Multiprocessing Bus Request pins
Bus Master Debug aid only
I/O Read pin
I/O Write pin
I/O Enable pin
Core Priority Access Hi to Low
Core Priority Access Low to Hi
DMA Priority Access Hi to Low
DMA Priority Access Low to Hi
Boot Memory Select
FLAG pins
Global Reset pin
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Data Output (JTAG)
Test Reset (JTAG)
Emulation High to Low
Static pins – must be constant
Static pins – must be constant
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
3.6
4.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
23.5
4.0
23.5
4.0
4.0
4.0
3.6
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.0
2.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.0
1.0
2.0
1.0
1.0
1.0
2.0
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
TCK
TCK
TCK
TCK
TCK or SCLK
SDCKE
RAS
CAS
SDWE
LDQM
HDQM
SDA10
HBR
HBG
BOFF
BUSLOCK
BRST
BR7–0
BM
IORD
IOWR
IOEN
CPA
DPA
BMS
FLAG3–0
2
RST_IN
3,4
TMS
TDI
TDO
TRST
3,4
EMU
5
ID2–0
6
CONTROLIMP1–0
6
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