參數(shù)資料
型號(hào)： ADSP-21992
廠商： Analog Devices, Inc.
英文描述： Mixed Signal DSP Controller With CAN
中文描述： 混合信號(hào)DSP控制器和CAN
文件頁(yè)數(shù)： 33/49頁(yè)
文件大小： 602K
代理商： ADSP-21992
PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
33
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
Serial Port (SPORT) Clocks and Data Timing
Table 12
and
Figure 20
describe SPORT transmit and receive operations.
Table 12. Serial Port (SPORT) Clocks and Data Timing
1
1
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
2
Referenced to drive edge.
3
Referenced to sample edge.
4
RFS hold after RCLK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCLK for late external TFS is 0 ns minimum from
drive edge.
Parameter
Description
Min
Max
Unit
Switching Characteristics
t
HOFSE
RFS Hold after RCLK (Internally Generated RFS)
2
0
12.4
ns
t
DFSE
RFS Delay after RCLK (Internally Generated RFS)
2
0
12.4
ns
t
DDTEN
Transmit Data Delay after TCLK
2
0
12.1
ns
t
DDTTE
Data Disable from External TCLK
2
0
12.0
ns
t
DDTIN
Data Enable from Internal TCLK
2
0
6.8
ns
t
DDTTI
Data Disable from Internal TCLK
2
0
6.3
ns
Timing Requirements
t
SCLKIW
TCLK/RCLK Width
20
ns
t
SFSI
TFS/RFS Setup before TCLK/RCLK
3
–0.6
ns
t
HFSI
TFS/RFS Hold after TCLK/RCLK
3, 4
–0.3
ns
t
SDRI
Receive Data Setup before RCLK
3
–2.3
ns
t
HDRI
Receive Data Hold after RCLK
3
1.9
ns
t
SCLKW
TCLK/RCLK Width
20
ns
t
SFSE
TFS/RFS Setup before TCLK/RCLK
3
–0.6
ns
t
HFSE
TFS/RFS Hold after TCLK/RCLK
3, 4
–0.6
ns
t
SDRE
Receive Data Setup before RCLK
3
–2.2
ns
t
HDRE
Receive Data Hold after RCLK
3
1.8
ns
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