參數(shù)資料
型號: ADSP-21992
廠商: Analog Devices, Inc.
英文描述: Mixed Signal DSP Controller With CAN
中文描述: 混合信號DSP控制器和CAN
文件頁數(shù): 17/49頁
文件大?。?/td> 602K
代理商: ADSP-21992
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
17
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
Layout Requirements
All JTAG signals (TCK, TMS, TDI, TDO, EMU, and
TRST) should be treated as critical route signals. This
means pay special attention when routing these signals.
Specify a controlled impedance requirement for each route
(value depends on your circuit board - typically 50-75 ).
Keep crosstalk and inductance to a minimum on these lines
by using a good ground plane and by routing away from
other high noise signals such as clock lines. Keep these
routes as short and clean as possible, and keep the bused
signals (TMS, TCK, TRST and, EMU) as close to the same
length as possible.
Note: The JTAG TAP relies on the state of the TMS line
and the TCK clock signal. If these signals have glitches (due
to ground bounce, crosstalk, etc.) unreliable emulator
operation will result. If you are experiencing emulator
problems, look at these signals using a high-speed digital
oscilloscope. These lines must be clean, and may require
special termination schemes. If you are buffering the JTAG
header (most customers will) you must provide signal ter-
mination appropriate for your target board (series, parallel,
R/C, etc.).
Power Sequence
The power-on sequence for your target and emulation
system is as follows: Apply power to the emulator first, then
to the target board. This ensures that the JTAG signals are
in the correct state for the DSP to run free. Upon power-on,
the emulator drives the TRST signal low, keeping the DSP
TAP in the test-logic-reset state, until the emulation
software takes control. Removal of power should be the
reverse: Turn off power to the target board then to the
emulator.
Emulator Model Specifics
The following sections contain design details on various
emulator pod designs by White Mountain DSP. The
emulator pod is the device that connects directly to the DSP
target board 14-pin JTAG header. Check our web site for
updates to this document that will contain new emulator
design details.
White Mountain DSP JTAG Pod Connector
This section applies to the Mountain ICE, Summit-ICE,
Trek-ICE, Mountain-ICE/WS, Apex-ICE.
Figure 10
details the dimensions of the JTAG pod connector
at the 14-pin target end.
Figure 11
displays the keep-out
area for a target board header. The keep-out area allows the
pod connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25” square post pin.
White Mountain DSP 3.3V Pod Logic
This section applies to Mountain ICE, Summit-ICE,
Trek-ICE, Mountain-ICE/WS, Apex-ICE.
A portion of the White Mountain DSP 3.3V emulator pod
interface is shown in
Figure 12
. This figure describes the
driver circuitry of the emulator pod. As can be seen, TMS,
TCK and TDI are driven with a 33
is driven with a 100 series resistor. TDO and CLKIN are
series resistor. TRST
Figure 9. Multiple-DSP JTAG-Connections, Buffered
EMU
TRST
E
T
E
T
T
T
TDI
TDO
E
T
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
GND
TMS
TCK
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
4
4
4
VDD
JTAG
CONNECTOR
DSP
P0
4
4
T
T
TDI
TDO
DSP
P1
DSP
P#
BUFFERS
T
T
TDI
TDO
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