參數(shù)資料
型號(hào)： ADSP-21992
廠商： Analog Devices, Inc.
英文描述： Mixed Signal DSP Controller With CAN
中文描述： 混合信號(hào)DSP控制器和CAN
文件頁(yè)數(shù)： 13/49頁(yè)
文件大?。?/td> 602K
代理商： ADSP-21992
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
13
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
Power Down All Mode
When the ADSP-21992 is in Power Down All mode, the
DSP core clock, the peripheral clock, and the PLL are all
stopped. The DSP does not retain the contents of the
instruction pipeline. The peripheral bus is stopped, so the
peripherals cannot receive data.
To exit Power Down Core/Peripherals mode, the DSP
responds to an interrupt and (after 500 cycles to re-stabilize
the PLL) resumes executing instructions.
Clock Signals
The ADSP-21992 can be clocked by a crystal oscillator or
a buffered, shaped clock derived from an external clock
oscillator. If a crystal oscillator is used, the crystal should be
connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in
Figure 5
. Capacitor
values are dependent on crystal type and should be specified
by the crystal manufacturer. A parallel resonant, fundamen-
tal frequency, microprocessor grade crystal should be used
for this configuration.
If a buffered, shaped clock is used, this external clock
connects to the DSP’s CLKIN pin. CLKIN input cannot
be halted, changed, or operated below the specified
frequency during normal operation. This clock signal
should be a TTL compatible signal. When an external clock
is used, the XTAL input must be left unconnected.
The DSP provides a user programmable 1 to 32 multi-
plication of the input clock, including some fractional
values, to support 128 external to internal (DSP core) clock
ratios. The BYPASS pin, and MSEL6–0 and DF bits, in the
PLL configuration register, decide the PLL multiplication
factor at reset. At runtime, the multiplication factor can be
controlled in software. To support input clocks greater that
100 MHz, the PLL uses an additional bit (DF). If the input
clock is greater than 100 MHz, DF must be set. If the input
clock is less than 100 MHz, DF must be cleared. For clock
multiplier settings, see the ADSP-21992
DSP Hardware
Reference Manual
.
The peripheral clock is supplied to the CLKOUT pin.
All on chip peripherals for the ADSP-21992 operate at the
rate set by the peripheral clock. The peripheral clock
(HCLK) is either equal to the core clock rate or one half the
DSP core clock rate (CCLK). This selection is controlled
by the IOSEL bit in the PLLCTL register. The maximum
core clock is 160 MHz, and the maximum peripheral clock
is 80 MHz—the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.
Reset and Power On Reset (POR)
The RESET pin initiates a complete hardware reset of the
ADSP-21992 when pulled low. The RESET signal must be
asserted when the device is powered up to assure proper
initialization. The ADSP-21992 contains an integrated
power on reset (POR) circuit that provides an output reset
signal, POR, from the ADSP-21992 on power up and if the
power supply voltage falls below the threshold level. The
ADSP-21992 may be reset from an external source using
the RESET signal or alternatively the internal power on
reset circuit may be used by connecting the POR pin to the
RESET pin. During power up the RESET line must be
activated for long enough to allow the DSP core's internal
clock to stabilize. The power up sequence is defined as the
total time required for the crystal oscillator to stabilize after
a valid VDD is applied to the processor and for the internal
phase locked loop (PLL) to lock onto the specific crystal
frequency. A minimum of 2000 cycles will ensure that the
PLL has locked (this does not include the crystal oscillator
start up time).
The RESET input contains some hysteresis. If using an RC
circuit to generate your RESET signal, the circuit should
use an external Schmidt trigger.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and resets all registers
to their default values (where applicable). When RESET is
released, if there is no pending bus request, program control
jumps to the location of the on chip boot ROM (0xFF0000)
and the booting sequence is performed.
Power Supplies
The ADSP-21992 has separate power supply connections
for the internal (V
DDINT
) and external (V
DDEXT
) power
supplies. The internal supply must meet the 2.5 V require-
ment. The external supply must be connected to a 3.3 V
supply. All external supply pins must be connected to the
same supply.
Figure 5. External Crystal Connections
CLKIN
XTAL
ADSP-2199X
50MHZ
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ADSP-21992BSTZ 功能描述:IC DSP CONTROLLER 16BIT 176LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
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ADSP-21992YST 制造商:Analog Devices 功能描述:
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