參數(shù)資料
型號: ADCS9888
廠商: National Semiconductor Corporation
英文描述: 205/170/140 MSPS Video Analog Front End
中文描述: 205/170/140 MSPS的視頻模擬前端
文件頁數(shù): 6/34頁
文件大?。?/td> 764K
代理商: ADCS9888
Pin Descriptions
(Continued)
Pin
Label
Type
Description
Data Clock Output
123
DATACK
Digital
Output
Data Output Clock. Complementary data clocks are provided so that output
data and HSOUT can be synchronously captured by external logic or
memory devices. The clock outputs are synchronous with the internal pixel
sample clock. As the sampling phase is adjusted, the DATACK, data, and
HSOUT signals all shift together with the sampling interval. When the chip
is in power down or seek mode, the DATACK outputs enter a high
impedance state.
Data Output Clock Invert. See DATACK description.
124
DATACK_B
Digital
Output
Data Outputs
113-120
D
R
_A(7:0)
Digital
Output
Red Port A (V or U/V) Output Data. Converted pixel data is presented at
the data output port synchronous with the DATACK and HSOUT signals.
As the pixel sample phase is adjusted, the HSOUT, DATACK and data
outputs all shift together. In single channel mode, all data is presented at
the A output ports. In dual channel mode, output data is presented at A
and B outputs, either in alternating (interleaved mode) or simultaneous
(parallel mode ) timing. When 4:2:2 pulldown mode is enabled, only the A
ports are used, with U/V data output on Red Port A, and Y data output on
Green Port A. When the chip is in seek mode, or low power mode, all data
outputs are placed in a high impedance state. See the applications section
and configuration registers section for more information.
Red Port B (V) Output Data. See D
R
_A(7:0).
103-110
D
R
_B(7:0)
Digital
Output
Digital
Output
Digital
Output
Digital
Output
Digital
Output
90-97
D
G
_A(7:0)
Green Port A (Y) Output Data. See D
R
_A(7:0).
80-87
D
G
_B(7:0)
Green Port B (Y) Output Datasheet. See D
R
_A(7:0).
70-77
D
B
_A(7:0)
Blue Port A (U) Output Data. See D
R
_A(7:0).
57-64
D
B
_B(7:0)
Blue Port B (U) Output Data. See D
R
_A(7:0).
Voltage Reference Bypass
2
REF
BYPASS
Analog
Bypass
Internal Reference Bypass. A 0.1 μF capacitor will be connected from this
pin to ground, to provide a low impedance decoupling for the internal
1.23V bandgap voltage reference.
Red (V) Channel midscale Voltage Bypass. No external bypass is required
for the midscale voltage. Therefore, this pin is not connected to the internal
circuitry. To maintain compatibility with other designs external capacitors
can be connected without affecting operation, performance, or reliability.
Blue (U) Channel midscale Voltage Bypass. No external bypass is required
for the midscale voltage. Therefore, this pin is not connected to the internal
circuitry. To maintain compatibility with other designs external capacitors
can be connected without affecting operation, performance, or reliability.
9
R
MIDSC
V
(NC)
Analog
Bypass
24
B
MIDSC
V
(NC)
Analog
Bypass
PLL Loop Filter
50
FILT
PLL VCO
Bypass
Phase Locked Loop - Voltage Controlled Oscillator filter connection. An
R/C filter circuit is used to maintain the VCO control voltage. This circuit
should be isolated from all other circuitry to minimize clock jitter. The circuit
is connected to the PV
D
bus to provide the maximum isolation from noisy
power and ground buses. Refer to the applications section for more
information.
A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADCS9888_05 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End
ADCS9888C WAF 制造商:Texas Instruments 功能描述:
ADCS9888CVH-140 制造商:Texas Instruments 功能描述:140MSPS VIDEO AFE 9888 TQFP128
ADCS9888CVH-140/NOPB 功能描述:IC VIDEO AFE 140MSPS 128-PQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率(瓦特):- 電壓 - 電源,模擬:3 V ~ 3.6 V 電壓 - 電源,數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN(5x5) 包裝:帶卷 (TR)
ADCS9888CVH-170 制造商:Texas Instruments 功能描述:IC 170MSPS VIDEO AFE 9888 TQFP64