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參數(shù)資料
| 型號： | ADCS9888 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 205/170/140 MSPS Video Analog Front End |
| 中文描述： | 205/170/140 MSPS的視頻模擬前端 |
| 文件頁數(shù)： | 4/34頁 |
| 文件大小： | 764K |
| 代理商： | ADCS9888 |
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Pin Descriptions
Pin
Label
Type
Description
Analog Video Inputs
5
R
AIN0
Analog
Input
Channel 0 Red (V) Video Input. Input for Red component video channel or
V chrominance channel in YUV/YPbPr/YCbCr applications. A high
impedance analog input. Input signal should be capacitively coupled to the
input using a 0.1 μF capacitor to support clamping and DC restoration.
Signal range of 0.5 V
PP
to 1.0 V
PP
depending on gain setting.
Channel 0 Green (Y) Video Input. Input for Green component video
channel or Y luminance channel in YUV/YPbPr/YCbCr applications. A high
impedance analog input. Input signal should be capacitively coupled to the
input using a 0.1 μF capacitor to support clamping and DC restoration.
Signal range of 0.5 V
PP
to 1.0 V
PP
depending on gain setting.
Channel 0 Blue (U) Video Input. Input for Blue component video channel
or U chrominance channel in YUV/YPbPr/YCbCr applications. A high
impedance analog input. Input signal should be capacitively coupled to the
input using a 0.1 μF capacitor to support clamping and DC restoration.
Signal range of 0.5 V
PP
to 1.0 V
PP
depending on gain setting.
Channel 1 Red (V) Video Input. See R
AIN0
for more information.
13
G
AIN0
Analog
Input
20
B
AIN0
Analog
Input
8
R
AIN1
Analog
Input
Analog
Input
Analog
Input
17
G
AIN1
Channel 1 Green (Y) Video Input. See G
AIN0
for more information.
23
B
AIN1
Channel 1 Blue (U) Video Input. See B
AIN0
for more information.
Analog Video Sync
12
SOGIN0
Analog
Input
Channel 0 Sync-On-Green-Input. A high impedance analog input. The
video channel containing synchronization information should be
capacitively coupled to this input using a 1.0 nF capacitor to support
negative peak clamping of the signal. When unused, this input should be
left unconnected.
Channel 1 Sync-On-Green-Input. See SOGIN0 for more information.
16
SOGIN1
Analog
Input
Sync/Clock Inputs
45
HSYNC0
Digital Input Channel 0 Horizontal Sync Input. A logic level synchronization signal at the
horizontal line rate is applied to this input. In applications where a
composite, logic level sync signal is present, that signal should be
connected to the HSYNC input. A Schmitt trigger input is used for
improved noise rejection. See the applications section for more
information.
Digital Input Channel 0 Vertical Sync Input. A logic level synchronization signal at the
vertical frame rate is applied to this input. A Schmitt trigger input is used
for improved noise rejection. See the applications section for more
information.
Digital Input Channel 1 Horizontal Sync Input. See HSYNC0 for more information.
Digital Input Channel 1 Vertical Sync Input. See VSYNC0 for more information.
Digital Input External CLAMP Timing Input. When enabled via Register OFh, Bit 7, this
input will turn on the clamp circuits in the analog video inputs. This signal
should be asserted during the black reference portion of the video
waveform. Please refer to the applications section for more information.
44
VSYNC0
43
42
30
HSYNC1
VSYNC1
CLAMP
A
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCS9888_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End |
| ADCS9888C WAF | 制造商:Texas Instruments 功能描述: |
| ADCS9888CVH-140 | 制造商:Texas Instruments 功能描述:140MSPS VIDEO AFE 9888 TQFP128 |
| ADCS9888CVH-140/NOPB | 功能描述:IC VIDEO AFE 140MSPS 128-PQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ADCS9888CVH-170 | 制造商:Texas Instruments 功能描述:IC 170MSPS VIDEO AFE 9888 TQFP64 |
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