參數(shù)資料
型號： ADCS9888
廠商： National Semiconductor Corporation
英文描述： 205/170/140 MSPS Video Analog Front End
中文描述： 205/170/140 MSPS的視頻模擬前端
文件頁數(shù)： 18/34頁
文件大?。?/td> 764K
代理商： ADCS9888
Configuration Register Descriptions
Address
(Hex)
00H
Write/Read
or Read Only
RO
Bits
POR Value
Name
Bit Name/Description
7:0
Revision
Chip Revision
8 bit value that indicates the silicon version. 00000000 =
Rev. 0
The upper 8 MSBs of the 12 bit PLL divider value.
Larger divisors cause the PLL to generate a higher
frequency clock. This register should be loaded first,
then register 02H, whenever the divider is changed. The
PLL divider value is only updated when the LSB value
in register 02H is updated. The actual PLL divider value
= (PLL register value + 1), so setting a value of 1055d
in registers 01H and 02H will result in a divide value of
1056.
Lower 4 LSBs of the 12 bit PLL divisor value. See
register 01H.
Sets the VCO frequency range for the desired pixel
rate.
00 = 15 - 41 MHz
01 = 41 - 82 MHz
10 = 82 - 150 MHz
11 = 150+ MHz
Sets the VCO charge pump current for the desired pixel
rate.
000 = 50 μA
001 = 100 μA
010 = 150 μA
011 = 250 μA
100 = 350 μA
101 = 500 μA
110 = 750 μA
111 = 1500 μA
5 bit value that adjusts the ADC sample timing relative
to HSYNC. LSB = 1/32 of one pixel period or 11.25
degrees of phase. The power up default value is 16D.
Sets the Clamp starting point N pixel periods after the
trailing edge of the Hsync signal. Settings from 1 to 255
are legal values for Clamp Placement. DO NOT SET =
0.
Clamp Duration Sets the Clamp duration to N pixel periods. Settings
from 1 to 255 are legal values. DO NOT SET = 0.
HSOUT
Pulsewidth
The leading edge of HSOUT is set by an internally
generated phase-adjusted PLL output. The chip then
counts the number of pixel periods set by HSOUT
Pulsewidth and triggers the trailing edge of HSOUT.
Red Gain
Controls the ADC input range for the RGB video inputs.
Default setting provides a nominal signal range of 0.7
V
PP
. Higher settings increase the signal range up to 1.0
V
PP
typ. Lower settings reduce the signal range to a
minimum of 0.5 V
PP
typ.
01H
W/R
7:0
01101001
PLL Divisor
MSB
02H
W/R
7:4
1101****
PLL Divisor
LSB
VCO
RNG/CPMP
03H
W/R
7:6
01******
5:3
**001***
04H
W/R
7:3
10000***
Sample Phase
Adjust
05H
W/R
7:0
00001000
Clamp
Placement
06H
W/R
7:0
00010100
07H
W/R
7:0
00100000
Sets the number of pixel periods that HSOUT is active.
08H
W/R
7:0
10000000
09H
W/R
7:0
10000000
Green Gain
0AH
W/R
7:0
10000000
Blue Gain
A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADCS9888_05 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End
ADCS9888C WAF 制造商:Texas Instruments 功能描述:
ADCS9888CVH-140 制造商:Texas Instruments 功能描述:140MSPS VIDEO AFE 9888 TQFP128
ADCS9888CVH-140/NOPB 功能描述:IC VIDEO AFE 140MSPS 128-PQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR)
ADCS9888CVH-170 制造商:Texas Instruments 功能描述:IC 170MSPS VIDEO AFE 9888 TQFP64
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