參數(shù)資料
型號(hào)： ADCS9888
廠商： National Semiconductor Corporation
英文描述： 205/170/140 MSPS Video Analog Front End
中文描述： 205/170/140 MSPS的視頻模擬前端
文件頁(yè)數(shù)： 27/34頁(yè)
文件大?。?/td> 764K
代理商： ADCS9888
Application Information
(Continued)
4.1.6 Pre-Coast and Post-Coast
When Vsync is used as the coast source, the coast signal
can be extended earlier and later by setting the Pre-Coast
and Post-Coast settings in Registers 12h and 13h. This
feature requires the chip to calculate the number of Hsync
pulses (lines) per Vsync (frame). An 11 bit counter is pro-
vided to support frame sizes up to 2048 lines (active lines
plus vertical blanking overhead).
Once the frame size has been calculated, the chip will an-
ticipate when the next VSYNC begins, and the coast signal
can be generated up to 255 lines earlier than the anticipated
Vsync. Similarly, the Post-coast setting allows the PLL coast
signal to be maintained as many as 255 lines following the
de-assertion of Vsync.
4.1.7 Coast Polarity Detection
The coast signal input to the Clock Generator can be an
active high or active low signal. A polarity detection circuit
determines the polarity of the Coast signal. The polarity is
determined by observing the high/low duty cycle of the
COAST signal to determine whether the signal is mostly high
or mostly low. If the signal is mostly low, then the polarity is
set as Positive. If the signal is mostly high, then the polarity
is set to Negative. (0 = Negative, 1 = Positive) The results of
this detection are sent to Register 14h, Bit 0.
Clock Generation Setting
Mode
Resolution
(Pixel/Lines)
Refresh
Rate
Hz
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
85
60
65
70
75
85
HSYNC
Frequency
kHz
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
91.1
75.0
81.3
87.5
93.8
106.3
Pixel
Rate
MHz
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
157.500
162.000
175.500
189.000
202.500
229.500
*
VCO
RNGE
VCO
CPMP
PLL
DIV Setting
VGA
640 x 480
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
11
11
11
11
11
10
010
011
011
011
011
011
011
011
011
011
100
100
011
011
011
101
100
100
100
100
101
101
799
831
839
831
1023
1055
1039
1055
1047
1343
1327
1311
1335
1375
1687
1687
1727
2159
2159
2159
2159
1079
SVGA
800 x 600
XGA
1024 x 768
SXGA
1280 x 1024
UXGA
1600 x 1200
Note:
* Alternate pixel sampling mode. See section 4.2.1
A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADCS9888_05 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End
ADCS9888C WAF 制造商:Texas Instruments 功能描述:
ADCS9888CVH-140 制造商:Texas Instruments 功能描述:140MSPS VIDEO AFE 9888 TQFP128
ADCS9888CVH-140/NOPB 功能描述:IC VIDEO AFE 140MSPS 128-PQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR)
ADCS9888CVH-170 制造商:Texas Instruments 功能描述:IC 170MSPS VIDEO AFE 9888 TQFP64
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