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參數(shù)資料
| 型號： | ADCS9888 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 205/170/140 MSPS Video Analog Front End |
| 中文描述： | 205/170/140 MSPS的視頻模擬前端 |
| 文件頁數(shù)： | 20/34頁 |
| 文件大小： | 764K |
| 代理商： | ADCS9888 |
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Configuration Register Descriptions
(Continued)
Address
(Hex)
0FH
Write/Read
or Read Only
W/R
Bits
POR Value
Name
Bit Name/Description
7
0*******
Clamp Control
Clamp Select. 0 = clamp timing determined by internal
chip counters derived from hsync. 1 = clamp timing
determined by external CLAMP signal.
CLAMP Polarity. 0 active high, 1 = active low. This bit
only has effect if Register 0FH, bit 7 = 1.
COAST Control COAST Select. 0 = COAST input pin is PLL coast
source. 1 = VSYNC is PLL coast source.
COAST Polarity Override. 0 = determined by chip. 1 =
determined by Register 0FH, bit 3.
COAST Polarity. 0 = active low, 1 = active high. This bit
only has an effect when Register 0FH, bit 5 = 0, and
Register 0FH bit 4 = 1.
Seek Override
Seek Mode Override. 0 = don’t allow low power mode.
1 = allow low power mode when sync inputs inactive. In
seek mode operation the HSOUT, VSOUT, DATACK
and DATACK, and all 48 data outputs are placed in a
high impedance state. The SOGOUT pin is still active.
The voltage references, sync detection and processing,
and serial register sub-system (for obvious reasons) are
maintained in an active state to provide a rapid
transition to normal operation.
PWRDN
Full chip power down. 0 = power down. 1 = normal
operation. In power down mode, the HSOUT, VSOUT,
DATACK, DATACK, and all 48 data outputs are placed
in a high impedance state. The SOGOUT pin is still
active. The voltage reference, sync detection and
processing, and serial register sub-system (for obvious
reasons) are maintained in an active state to provide a
rapid transition to normal operation.
Sync-On-Green
Threshold
LSB size is 10 mV. Setting of 00h gives a nominal
threshold of 10 mV, while maximum setting of 1FH
gives a nominal threshold of 330 mV. Optimal settings
will be lower than those used with the Analog Devices
AD9888.
Red Clamp
Select
Blue Clamp
Select
Sync Separator
Threshold
separator will count to before toggling high or low. This
value should be set to some amount greater than the
widest expected hsync or equalization pulse width.
Pre-coast
Sets the number of Hsync periods that the PLL coast
becomes active prior to Vsync. This setting is only valid
when Vsync is used as the PLL coast source.
Post-Coast
Sets the number of Hsync periods that the PLL coast
stays active after Vsync becomes inactive. This setting
is only valid when Vsync is used as the PLL coast
source.
6
*1******
5
**0*****
4
***0****
3
****1***
2
*****1**
1
******1*
10H
W/R
7:3
01111***
Set the voltage of the sync slicer threshold. 00H to 1FH.
2
*****0**
0 = clamp to ground. 1 = clamp to R
MIDSC
V.
1
******0*
0 = clamp to ground. 1 = clamp to B
MIDSC
V.
11H
W/R
7:0
00100000
Sets how many internal 5 MHz clock periods the sync
12H
W/R
7:0
00000000
13H
W/R
7:0
00000000
A
www.national.com
20
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADCS9888_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End |
| ADCS9888C WAF | 制造商:Texas Instruments 功能描述: |
| ADCS9888CVH-140 | 制造商:Texas Instruments 功能描述:140MSPS VIDEO AFE 9888 TQFP128 |
| ADCS9888CVH-140/NOPB | 功能描述:IC VIDEO AFE 140MSPS 128-PQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ADCS9888CVH-170 | 制造商:Texas Instruments 功能描述:IC 170MSPS VIDEO AFE 9888 TQFP64 |
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