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參數(shù)資料
| 型號(hào)： | ADCS9888 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 205/170/140 MSPS Video Analog Front End |
| 中文描述： | 205/170/140 MSPS的視頻模擬前端 |
| 文件頁數(shù)： | 28/34頁 |
| 文件大?。?/td> | 764K |
| 代理商： | ADCS9888 |
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Application Information
(Continued)
4.2 Pixel Clock Generation And Timing AdjustmenT
Several features are provided that are related to the pixel
clock timing. These include:
Clock Phase Adjust
CKINV - This is discussed in more detail in the next
section, “CKINV Input”.
Clamp Placement setting
Clamp Duration setting
Please refer to the register description table for more details
on these adjustments.
4.2.1 CKINV Input
This is a digital input that causes the ADC sampling clock to
be inverted. In effect, this causes an additional 180 degrees
of phase shift in the ADC sampling point. This input is used
in support of Alternate Pixel Sampling mode, which allows
higher frequency video signals to be captured. In this mode,
only every second pixel is sampled and converted. This is
easily achieved by setting the PLL divider value to achieve
one half of the true video pixel rate. On one video frame, all
odd video pixels will be converted and sent to the video
processor. On the next video frame, the state of CKINV will
be inverted, and all even pixels will be converted and output.
Frame re-assembly and display will be performed by the
video scaler or other video processing system.
This input should only change state during the vertical blank-
ing interval, as it may produce several samples of corrupted
ADC data during the phase shift. This input should be con-
nected to ground when not in use.
4.2.2 CKEXT Input
While most applications will use the built in PLL to generate
a pixel clock, in some cases, the user will drive the CKEXT
input with an external pixel clock source. In these applica-
tions, the PLL is not used and will be placed in a minimum
power state.
The ADC Sample Phase adjustment is available when CK-
EXT is used.
5.0 TIMING OUTPUTS
5.1 SOGOUT
This pin outputs either the output from the sync slicer, or a
delayed but unprocessed version of the HSYNC input. The
signal at SOGOUT is the same polarity as the input signal.
5.2 HSOUT
This pin outputs a reconstructed and phase aligned version
of the HSYNC input. Both the polarity and duration of this
signal are controlled via register settings.
5.3 VSOUT
This pin outputs a delayed but unprocessed (except for
selectable inversion via register 0Eh, bit 3) version of the
vertical sync signal. This signal can be selected from either
the VSYNC input, or the output of the Sync Separator.
5.4 DATACK/DATACKB
These pins provide a complementary output pixel clock that
will be used to capture the digital data and HSOUT into the
connected digital logic. The output frequency of the clock is
dependent on the data output mode being used. Refer to the
description for register 15h.
6.0 CONFIGURATION REGISTERS
All device settings are controlled via the configuration regis-
ters. These registers are accessed via a serial control bus
which consists of 3 inputs/outputs (Serial Data, Serial Clock
and A0).
6.1 Serial Control Interface
The serial control interface consists of a bi-directional Data
line and an input only Clock line. All clock information is
controlled by the Master or Host device, which will usually be
a microcontroller or microprocessor. The data line will be
driven by the Master or Host during the control/address
portions of the protocol. Data portions of the transfer can be
driven by either the Master or the ADCS9888, depending on
the direction of data flow. The two bus lines will have pullup
resistors to a power supply bus, and all devices connected to
the bus will use open-drain drivers to activate the clock and
data lines. This allows multiple Master and Slave devices to
coexist on the same serial interface without bus contention.
6.2 Serial Protocol
The serial protocol is made up of a number of basic protocol
elements. A typical transaction will consist of:
Start Signal
(Slave Address + Read/Write Bit) Byte
Base Register Address Byte
Data Byte
Stop Signal
6.2.1 Start Signal
Initially, when the bus is inactive, both SCL and SDA will be
in a high logic state. A start signal consists of the SDA line
transitioning from high to low, while the SCL line remains
high.
6.2.2 Stop Signal
When the bus is active, the data line will normally be high or
low, and the clock will transition from low, to high, then return
to low, to register the next bit in the sequence. A stop signal
consists of the SDA line transitioning to a low state, followed
by the SCL line transitioning to a high state, followed by the
SDA line transitioning to the high state.
6.2.3 Repeat Start Signal
A repeat start occurs in a sequence where a slave address
and base address have already been transferred, but the
mode of communications will be changing from Write to
Read. This occurs during Read operations, since any Read
operation first begins with a Write to specify the base register
address.
6.2.4 Slave Address BYTE
The slave address byte is used to distinguish between the
different devices that may be connected to a common serial
bus. Devices have a 7 bit address, with many devices having
some bits configurable via external pin connections. The
ADCS9888 address byte is configured as follows:
A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCS9888_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End |
| ADCS9888C WAF | 制造商:Texas Instruments 功能描述: |
| ADCS9888CVH-140 | 制造商:Texas Instruments 功能描述:140MSPS VIDEO AFE 9888 TQFP128 |
| ADCS9888CVH-140/NOPB | 功能描述:IC VIDEO AFE 140MSPS 128-PQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ADCS9888CVH-170 | 制造商:Texas Instruments 功能描述:IC 170MSPS VIDEO AFE 9888 TQFP64 |
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