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參數(shù)資料
| 型號(hào)： | ADCS9888 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 205/170/140 MSPS Video Analog Front End |
| 中文描述： | 205/170/140 MSPS的視頻模擬前端 |
| 文件頁數(shù)： | 26/34頁 |
| 文件大?。?/td> | 764K |
| 代理商： | ADCS9888 |
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Application Information
(Continued)
4.1 PLL
The PLL generates a high frequency pixel clock that is
frequency locked and phase aligned to the horizontal sync
signal.
The main controls for the PLL are as described in the follow-
ing subsections.
4.1.1 PLL Divider
The PLL divider is a 12 bit counter with an adjustment range
of 17 to 4096. The divider setting is configured in registers
01h, and 02h. The actual divider value used is the divider
register setting + 1, so loading a value of 1055 decimal
results in a divider of 1056. The PLL divider value sets the
number of pixel periods per line. This value consists of the
active video pixels, plus the horizontal blanking overhead.
The overhead is typically 20 to 30% of the total line time.
VESA (Video Equipment Standards Association) has estab-
lished a series of standards for the different computer video
settings (resolution and frame rate). These can be used to
determine the proper settings of the PLL divider for many
applications. Some applications will use non-standard video
timings. In these cases, more advanced methods will be
required to determine the proper divider setting to use.
The power up default value of the PLL divide registers is
1693d for a real divider setting of 1694d.
4.1.2 VCO Filter Circuit
The Voltage Controlled Oscillator uses an external filter cir-
cuit to smooth the charge pump current pulses, and optimize
the VCO performance. This circuit connects between the
FILT pin and PVD power bus. The filter circuit, and the PVD
power must be well isolated from other circuitry to achieve
the best PLL performance and low jitter.
20062821
4.1.3 VCO Frequency Range Control
The VCO frequency range setting selects the gain of the
VCO. By optimizing the gain, the VCO performance can be
optimized for different operating frequency ranges. The
value is set via the two most significant bits of register 03h.
PV1
PV0
Pixel
Clock
Range
(MHz)
15-41
41-82
82-150
K
VCO
Gain
(MHz/V)
0
0
1
0
1
0
31
61
122
PV1
PV0
Pixel
Clock
Range
(MHz)
>
150
K
VCO
Gain
(MHz/V)
1
1
200
4.1.4 VCO Charge Pump Current Control
The PLL charge pump current can be set to different values
to help optimize the performance for different frequency
ranges of operation. The value is set via bits 5:3 of Register
03h.
IP2
IP1
IP0
Charge Pump
Current (μA)
50
100
150
250
350
500
750
1500
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The VCO charge pump current can be calculated using the
following equation, and the values for Kvco from the table in
the previous section.
Ip = [(HsyncFreq x 2 x
π
)/19.2]
^
2 x [(Ct x N)/Kvco)]
Where:
Ip = Target Charge Pump current. Round this value up to the
next highest available setting.
HsyncFreq = Frequency of Hsync reference clock
π
= 3.1415927 (approximately)
19.2 = The PLL stability ratio for the ADCS9888
Ct = Loop filter capacitance
N = PLL divider value (register setting in 04h, 05h +1)
Kvco = VCO gain in MHz/V
4.1.5 PLL Coast
The PLL clock generator provides a high frequency pixel
clock that is phase aligned to the horizontal sync signal.
During portions of the video signal, this horizontal sync
signal may be absent or may have a frequency that is
different than the "normal" frequency. During these times,
application of the coast signal to the PLL causes it to main-
tain its current operating frequency and phase (according to
the voltage held on the VCO filter capacitor) and “coast”,
without attempting to synchronize with the horizontal sync
waveform. When the coast signal is de-asserted, the PLL will
again try to phase lock with the horizontal sync input.
In most applications, the coast signal is derived from the
vertical synchronization pulse from the VSYNC input or from
one of the composite sync sources (either SOGIN or
HSYNC) after being processed in the sync separator.
The COAST input allows the user to provide a separate
external coast control signal. Register 0Fh, bit 5 is used to
select which source is used.
A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCS9888_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:205/170/140 MSPS Video Analog Front End |
| ADCS9888C WAF | 制造商:Texas Instruments 功能描述: |
| ADCS9888CVH-140 | 制造商:Texas Instruments 功能描述:140MSPS VIDEO AFE 9888 TQFP128 |
| ADCS9888CVH-140/NOPB | 功能描述:IC VIDEO AFE 140MSPS 128-PQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ADCS9888CVH-170 | 制造商:Texas Instruments 功能描述:IC 170MSPS VIDEO AFE 9888 TQFP64 |
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